Master-Slave Match Line Design for Low-Power Content-Addressable Memory.
Yen-Jen ChangTung-Chi WuPublished in: IEEE Trans. Very Large Scale Integr. Syst. (2015)
Keyphrases
- low power
- master slave
- high speed
- single chip
- low cost
- power consumption
- low power consumption
- vlsi architecture
- logic circuits
- digital signal processing
- power dissipation
- gate array
- power reduction
- ultra low power
- efficient implementation
- mixed signal
- vlsi circuits
- design process
- cmos technology
- digital circuits
- high power
- parallel processing