Yasumitsu Orii

Publication Activity (10 Years)

Years Active: 2004-2023
Publications (10 Years): 5

Top Topics

Primary Purpose

Top Venues

Publications

Yasumitsu Orii
Semiconductor Packaging Revolution in the Era of Chiplets. ICICDT (2023)
Yasumitsu Orii
Semiconductor Packaging Revolution in the Era of Chiplets : Keynote 1. ITC-Asia (2023)
Seiji Takeda, Toshiyuki Hama, Hsiang-Han Hsu, Victoria A. Piunova, Dmitry Zubarev, Daniel P. Sanders, Jed W. Pitera, Makoto Kogoh, Takumi Hongo, Yenwei Cheng, Wolf Bocanett, Hideaki Nakashika, Akihiro Fujita, Yuta Tsuchiya, Katsuhiko Hino, Kentaro Yano, Shuichi Hirose, Hiroki Toda, Yasumitsu Orii, Daiju Nakano
Molecular Inverse-Design Platform for Material Industries. CoRR (2020)
Seiji Takeda, Toshiyuki Hama, Hsiang-Han Hsu, Victoria A. Piunova, Dmitry Zubarev, Daniel P. Sanders, Jed W. Pitera, Makoto Kogoh, Takumi Hongo, Yenwei Cheng, Wolf Bocanett, Hideaki Nakashika, Akihiro Fujita, Yuta Tsuchiya, Katsuhiko Hino, Kentaro Yano, Shuichi Hirose, Hiroki Toda, Yasumitsu Orii, Daiju Nakano
Molecular Inverse-Design Platform for Material Industries. KDD (2020)
Matteo Manica, Christoph Auer, Valéry Weber, Federico Zipoli, Michele Dolfi, Peter W. J. Staar, Teodoro Laino, Costas Bekas, Akihiro Fujita, Hiroki Toda, Shuichi Hirose, Yasumitsu Orii
An Information Extraction and Knowledge Graph Platform for Accelerating Biochemical Discoveries. CoRR (2019)
Kuniaki Sueoka, Akihiro Horibe, T. Aoki, Sayuri Kohara, Kazushige Toriyama, Hiroyuki Mori, Yasumitsu Orii
Vertical integration after stacking (ViaS) process for low-cost and low-stress 3D silicon integration. 3DIC (2015)
Keiji Matsumoto, Hiroyuki Mori, Yasumitsu Orii
Cooling from the bottom side (laminate (substrate) side) of a three-dimensional (3D) chip stack. 3DIC (2014)
Sayuri Kohara, Akihiro Horibe, Kuniaki Sueoka, Keiji Matsumoto, Fumiaki Yamada, Hiroyuki Mori, Yasumitsu Orii
Thermo-mechanical evaluation of 3D packages. 3DIC (2013)
Keiji Matsumoto, Soichiro Ibaraki, Kuniaki Sueoka, Katsuyuki Sakuma, Hidekazu Kikuchi, Hiroyuki Mori, Yasumitsu Orii, Fumiaki Yamada, Kohei Fujihara, Junichi Takamatsu, Koji Kondo
Thermal design guideline and new cooling solution for a three-dimensional (3D) chip stack. 3DIC (2013)
Toru Ikeda, Masatoshi Oka, Shinya Kawahara, Noriyuki Miyazaki, Keiji Matsumoto, Sayuri Kohara, Yasumitsu Orii, Fumiaki Yamada, Morihiro Kada
Combination between the nonlinear finite element analyses and the strain measurement using the digital image correlation for a new 3D SIC package. 3DIC (2011)
Sayuri Kohara, Akihiro Horibe, Kuniaki Sueoka, Keiji Matsumoto, Fumiaki Yamada, Yasumitsu Orii, Katsuyuki Sakuma, Takahiro Kinoshita, Takashi Kawakami
Thermal stress analysis of die stacks with fine-pitch IMC interconnections for 3D integration. 3DIC (2011)
Akihiro Horibe, Kuniaki Sueoka, Katsuyuki Sakuma, Sayuri Kohara, Keiji Matsumoto, Hidekazu Kikuchi, Yasumitsu Orii, Toshiro Mitsuhashi, Fumiaki Yamada
High density 3D integration by pre-applied Inter Chip Fill. 3DIC (2010)
Ikuo Shohji, Hideo Mori, Yasumitsu Orii
Solder joint reliability evaluation of chip scale package using a modified Coffin-Manson equation. Microelectron. Reliab. 44 (2) (2004)