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Solder joint reliability evaluation of chip scale package using a modified Coffin-Manson equation.

Ikuo ShohjiHideo MoriYasumitsu Orii
Published in: Microelectron. Reliab. (2004)
Keyphrases
  • high speed
  • failure rate
  • low cost
  • scale space
  • evaluation model
  • numerical solution
  • printed circuit boards
  • neural network
  • mathematical model
  • vlsi design