Stephen Y. H. Su

Publication Activity (10 Years)

Years Active: 1971-1997
Publications (10 Years): 0

Publications

Stephen Y. H. Su, Rong Yao
Fault-Tolerant Array Processors Via Reconfiguration of Two-Level Redundancy Arrays. PDPTA (1997)
Michal Cutler, Stephen Y. H. Su, Mingshien Wang
Distributed self-diagnosis of VLSI mesh array processors. VTS (1991)
Stephen Y. H. Su, Michal Cutler, Mingshien Wang
Self-Diagnosis of Faelures in VLSI Tree Array Processors. IEEE Trans. Computers 40 (11) (1991)
Mingshien Wang, Michal Cutler, Stephen Y. H. Su
Reconfiguration of VLSI/WSI Mesh Array Processors with Two-Level Redundancy. IEEE Trans. Computers 38 (4) (1989)
Stephen Y. H. Su, Hede Ma
Fault Isolation in Grey Systems. ITC (1988)
Stephen Y. H. Su, Hede Ma
Designs for Diagnosability and Reliability in VLSI Systems. ITC (1988)
Li Shen, Stephen Y. H. Su
A Functional Testing Method for Microprocessors. IEEE Trans. Computers 37 (10) (1988)
Israel Koren, Zahava Koren, Stephen Y. H. Su
Analysis of a Class of Recovery Procedures. IEEE Trans. Computers 35 (8) (1986)
Tonysheng Lin, Stephen Y. H. Su
VLSI Functional Test Pattern Generation: A Design and Implementation. ITC (1985)
Tonysheng Lin, Stephen Y. H. Su
The S-Algorithm: A Promising Solution for Systematic Functional Test Generation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 4 (3) (1985)
Shiyi Xu, Stephen Y. H. Su
Detecting I/O and Internal Feedback Bridging Faults. IEEE Trans. Computers 34 (6) (1985)
Stephen Y. H. Su, Tonysheng Lin
Functional testing techniques for digital LSI/VLSI systems. DAC (1984)
Li Shen, Stephen Y. H. Su
VLSI functional testing using critical path traces at hardware description language level. Fehlertolerierende Rechensysteme (1984)
Tonysheng Lin, Stephen Y. H. Su
Functional Test Generation of Digital LSI/VLSI Systems Using Machine Symbolic Execution Technique. ITC (1984)
Stephen Y. H. Su
IDAS: an integrated design automation system. AFIPS National Computer Conference (1984)
Kewal K. Saluja, Li Shen, Stephen Y. H. Su
A Simplified Algorithm for Testing Microprocessors. ITC (1983)
Yinghua Min, Stephen Y. H. Su
Testing functional faults in VLSI. DAC (1982)
Yashwant K. Malaiya, Stephen Y. H. Su
A New Fault Model and Testing Technique for CMOS Devices. ITC (1982)
Yacoub M. El-Ziq, Stephen Y. H. Su
Fault Diagnosis of MOS Combinational Networks. IEEE Trans. Computers 31 (2) (1982)
Chi-Chang Liaw, Stephen Y. H. Su, Yashwant K. Malaiya
State Diagram Approach for Functional Testing of Control Section. ITC (1981)
Chi-Chang Liaw, Stephen Y. H. Su, Yashwant K. Malaiya
Test-Experiments for Detection and Location of Intermittent Faults in Sequential Circuits. IEEE Trans. Computers 30 (12) (1981)
Yashwant K. Malaiya, Stephen Y. H. Su
Reliability Measure of Hardware Redundancy Fault-Tolerant Digital Systems with Intermittent Faults. IEEE Trans. Computers 30 (8) (1981)
Stephen Y. H. Su, Yu-I Hsieh
Testing Functional Faults in Digital Systems Described by Register Transfer Language. ITC (1981)
Stephen Y. H. Su, Edgar DuCasse
A Hardware Redundancy Reconfiguration Scheme for Tolerating Multiple Module Failures. IEEE Trans. Computers 29 (3) (1980)
Mark G. Karpovsky, Stephen Y. H. Su
Detecting bridging and stuck-at faults at input and output pins of standard digital components. DAC (1980)
Mark G. Karpovsky, Stephen Y. H. Su
Detection and Location of Input and Feedback Bridging Faults Among Input and Output Lines. IEEE Trans. Computers 29 (6) (1980)
Israel Koren, Stephen Y. H. Su
-Modular Redundancy Systems with Intermittent and Permanent Faults. IEEE Trans. Computers 28 (7) (1979)
Yashwant K. Malaiya, Stephen Y. H. Su
A survey of methods for intermittent fault analysis. MARK (1979)
Yacoub M. El-Ziq, Stephen Y. H. Su
Computer-Aided Logic Design of Two-Level MOS Combinational Networks with Statistical Results. IEEE Trans. Computers 27 (10) (1978)
John G. Yee, Stephen Y. H. Su
A scheme for tolerating faulty data in real-time systems. COMPSAC (1978)
Stephen Y. H. Su, Israel Koren, Yashwant K. Malaiya
A Continous-Parameter Markov Model and Detection Procedures for Intermittent Faults. IEEE Trans. Computers 27 (6) (1978)
Stephen Y. H. Su
Hardware Description Language Applications: An Introdiction and Prognosis. Computer 10 (6) (1977)
Yacoub M. El-Ziq, Stephen Y. H. Su
Logic design automation of diagnosable MOS combinational logic networks. DAC (1977)
Richard J. Spillman, Stephen Y. H. Su
Detection of Single, Stuck-Type Faulures in Multivalued Combinational Networks. IEEE Trans. Computers 26 (12) (1977)
Stephen Y. H. Su, Richard J. Spillman
An overview of fault-tolerant digital system architecture. AFIPS National Computer Conference (1977)
Melvin A. Breuer, Shih-Jeh Chang, Stephen Y. H. Su
Identification of Multiple Stuck-Type Faults in Combinational Networks. IEEE Trans. Computers 25 (1) (1976)
Stephen Y. H. Su
An introduction to CHDL (computer hardware description languages). SIGARCH Comput. Archit. News 4 (3) (1975)
Stephen Y. H. Su
A survey of computer hardware description languages in the U.S.A. Computer 7 (12) (1974)
Stephen Y. H. Su
Speculation on the future of design automation. DAC (1974)
Stephen Y. H. Su
Book review of Logic and logic design by B. Girling and H. G. Morning. International Textbook Company Limited 1973. SIGARCH Comput. Archit. News 3 (3) (1974)
Stephen Y. H. Su
Review of "Asynchronous Sequential Switching Circuits" by S. H. Unger. IEEE Trans. Syst. Man Cybern. 3 (3) (1973)
Stephen Y. H. Su
B73-12 Fault Detection in Digital Circuits. IEEE Trans. Computers 22 (5) (1973)
Stephen Y. H. Su
Review of "Fault Diagnosis of Digital Systems" by H. Y. Chang, E. G. Manning, and G. Metze. IEEE Trans. Syst. Man Cybern. 3 (3) (1973)
Stephen Y. H. Su
An interactive design automation system. DAC (1973)
Stephen Y. H. Su, Peter T. Cheung
Computer Minimization of Multivalued Switching Functions. IEEE Trans. Computers 21 (9) (1972)
Stephen Y. H. Su, Achilles A. Sarris
The Relationship Between Multivalued Switching Algebra and Boolean Algebra Under Different Definitions of Complement. IEEE Trans. Computers 21 (5) (1972)
Stephen Y. H. Su, Yun-Chung Cho
A New Approach to the Fault Location of Combinational Circuits. IEEE Trans. Computers 21 (1) (1972)
Stephen Y. H. Su, Chong-Woo Nam
Computer-Aided Synthesis or Multiple-Output Multilevel NAND Networks witk Fan-in and Fan-out Constraints. IEEE Trans. Computers 20 (12) (1971)
Mehmet Baray, Stephen Y. H. Su
A digital system modeling philosophy and design language. DAC (1971)
Stephen Y. H. Su, Mehmet Baray, Robert L. Carberry
A system modeling language translator. DAC (1971)
Mehmet Baray, Stephen Y. H. Su, Robert L. Carberry
The structure and operation of a design language compatible simulator. DAC (1971)