Roshan Weerasekera

Publication Activity (10 Years)

Years Active: 2004-2024
Publications (10 Years): 5

Top Topics

Transmission Line

Carbon Nanotubes

Navier Stokes Equations

User Oriented Evaluation

Top Venues

IEEE Trans. Circuits Syst. I Regul. Pap.

Publications

Disala Uduwawala, Roshan Weerasekera
Incident and Load Power Relations in a Mismatched Lossless Transmission Line. Circuits Syst. Signal Process. 43 (9) (2024)
Richard Mayne, Nic Roberts, Neil Phillips, Roshan Weerasekera, Andrew Adamatzky
Propagation of electrical signals by fungi. Biosyst. 229 (2023)
Richard Mayne, Nic Roberts, Neil Phillips, Roshan Weerasekera, Andrew Adamatzky
Propagation of electrical signals by fungi. CoRR (2023)
Richard Mayne, Thomas C. Draper, Neil Phillips, James Gerald Holland Whiting, Roshan Weerasekera, Claire Fullarton, Ben P. J. de Lacy Costello, Andrew Adamatzky
Neuromorphic Liquid Marbles With Aqueous Carbon Nanotube Cores. CoRR (2019)
Andrew Adamatzky, Neil Phillips, Roshan Weerasekera, Michail-Antisthenis I. Tsompanas, Georgios Ch. Sirakoulis
Excitable London: Street map analysis with Oregonator model. CoRR (2018)
Chao Wang, Jun Zhou, Roshan Weerasekera, Bin Zhao, Xin Liu, Philippe Royannez, Minkyu Je
BIST Methodology, Architecture and Circuits for Pre-Bond TSV Testing in 3D Stacking IC Systems. IEEE Trans. Circuits Syst. I Regul. Pap. (1) (2015)
Guruprasad Katti, S. W. Ho, Li Hong Yu, Songbai Zhang, Rahul Dutta, Roshan Weerasekera, Ka-Fai Chang, Jong-Kai Lin, Srinivasa Rao Vempati, Surya Bhattacharya
Fabrication and Assembly of Cu-RDL-Based 2.5-D Low-Cost Through Silicon Interposer (LC-TSI). IEEE Des. Test 32 (4) (2015)
Jiacheng Wang, Shunli Ma, Sai Manoj Pudukotai Dinakarrao, Mingbin Yu, Roshan Weerasekera, Hao Yu
High-speed and low-power 2.5D I/O circuits for memory-logic-integration by through-silicon interposer. 3DIC (2013)
Yuhao Wang, Chun Zhang, Revanth Nadipalli, Hao Yu, Roshan Weerasekera
Design exploration of 3D stacked non-volatile memory by conductive bridge based crossbar. 3DIC (2011)
Dinesh Pamunuwa, Matthew Grange, Roshan Weerasekera, Axel Jantsch
3-D integration and the limits of silicon computation. VLSI-SoC (2011)
Joseph Romen Cubillo, Roshan Weerasekera, Zaw Zaw Oo, En-Xiao Liu, Bob Conn, Surya Bhattacharya, Robert Patti
Interconnect design and analysis for Through Silicon Interposers (TSIs). 3DIC (2011)
Matt Grange, Roshan Weerasekera, Dinesh Pamunuwa, Axel Jantsch, Awet Yemane Weldezion
Optimal network architectures for minimizing average distance in k-ary n-dimensional mesh networks. NOCS (2011)
Matthew Grange, Axel Jantsch, Roshan Weerasekera, Dinesh Pamunuwa
Modeling the computational efficiency of 2-D and 3-D silicon processors for early-chip planning. ICCAD (2011)
Roshan Weerasekera, Matt Grange, Dinesh Pamunuwa, Hannu Tenhunen
On signalling over Through-Silicon Via (TSV) interconnects in 3-D Integrated Circuits. DATE (2010)
Awet Yemane Weldezion, Zhonghai Lu, Roshan Weerasekera, Hannu Tenhunen
3-D memory organization and performance analysis for multi-processor network-on-chip architecture. 3DIC (2009)
Roshan Weerasekera, Dinesh Pamunuwa, Li-Rong Zheng, Hannu Tenhunen
Two-Dimensional and Three-Dimensional Integration of Heterogeneous Electronic Systems Under Cost, Performance, and Technological Constraints. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28 (8) (2009)
Awet Yemane Weldezion, Matt Grange, Dinesh Pamunuwa, Zhonghai Lu, Axel Jantsch, Roshan Weerasekera, Hannu Tenhunen
Scalability of network-on-chip communication architecture for 3-D meshes. NOCS (2009)
Matt Grange, Awet Yemane Weldezion, Dinesh Pamunuwa, Roshan Weerasekera, Zhonghai Lu, Axel Jantsch, Dave Shippen
Physical mapping and performance study of a multi-clock 3-Dimensional Network-on-Chip mesh. 3DIC (2009)
Roshan Weerasekera, Matt Grange, Dinesh Pamunuwa, Hannu Tenhunen, Li-Rong Zheng
Compact modelling of Through-Silicon Vias (TSVs) in three-dimensional (3-D) integrated circuits. 3DIC (2009)
Roshan Weerasekera, Dinesh Pamunuwa, Li-Rong Zheng, Hannu Tenhunen
Minimal-Power, Delay-Balanced Smart Repeaters for Global Interconnects in the Nanometer Regime. IEEE Trans. Very Large Scale Integr. Syst. 16 (5) (2008)
Roshan Weerasekera, Dinesh Pamunuwa, Li-Rong Zheng, Hannu Tenhunen
Delay-Balanced Smart Repeaters for On-Chip Global Signaling. VLSI Design (2007)
Roshan Weerasekera, Li-Rong Zheng, Dinesh Pamunuwa, Hannu Tenhunen
Extending systems-on-chip to the third dimension: performance, cost and technological tradeoffs. ICCAD (2007)
Roshan Weerasekera, Li-Rong Zheng, Dinesh Pamunuwa, Hannu Tenhunen
Early selection of system implementation choice among SoC, SoP and 3-D Integration. SoCC (2007)
Roshan Weerasekera, Dinesh Pamunuwa, Li-Rong Zheng, Hannu Tenhunen
Minimal-power, delay-balanced smart repeaters for interconnects in the nanometer regime. SLIP (2006)
Roshan Weerasekera, Li-Rong Zheng, Dinesh Pamunuwa, Hannu Tenhunen
Switching Sensitive Driver Circuit to Combat Dynamic Delay in On-Chip Buses. PATMOS (2005)
Roshan Weerasekera, Li-Rong Zheng, Dinesh Pamunuwa, Hannu Tenhunen
Crosstalk immune interconnect driver design. SoC (2004)