Philippe Royannez

Publication Activity (10 Years)

Years Active: 1996-2015
Publications (10 Years): 0

Top Topics

Ensemble Learning

Computing Systems

Computationally Demanding

Top Venues

IEEE Trans. Circuits Syst. I Regul. Pap.

Publications

Chao Wang, Jun Zhou, Roshan Weerasekera, Bin Zhao, Xin Liu, Philippe Royannez, Minkyu Je
BIST Methodology, Architecture and Circuits for Pre-Bond TSV Testing in 3D Stacking IC Systems. IEEE Trans. Circuits Syst. I Regul. Pap. (1) (2015)
Zhaohui Hu, Arnaud Pierres, Shiqing Hu, Chen Fang, Philippe Royannez, Eng Pek See, Yean Ling Hoon
Practical and efficient SOC verification flow by reusing IP testcase and testbench. ISOCC (2012)
Gordon Gammie, Alice Wang, Hugh Mair, Rolf Lagerquist, Minh Chau, Philippe Royannez, Sumanth Gururajarao, Uming Ko
SmartReflex Power and Performance Management Technologies for 90 nm, 65 nm, and 45 nm Mobile Application Processors. Proc. IEEE 98 (2) (2010)
Gordon Gammie, Alice Wang, Minh Chau, Sumanth Gururajarao, Robert Pitts, Fabien Jumel, Stacey Engel, Philippe Royannez, Rolf Lagerquist, Hugh Mair, Jeff Vaccani, Greg Baldwin, Keerthi Heragu, Rituparna Mandal, Michael Clinton, Don Arden, Uming Ko
A 45nm 3.5G Baseband-and-Multimedia Application Processor using Adaptive Body-Bias and Ultra-Low-Power Techniques. ISSCC (2008)
Philippe Royannez, Hugh Mair, Michael Clinton, Uming Ko
Solutions for logic and processor core design at the 45nm technology node & and below. ICECS (2007)
Chris Van Hoof, Philippe Royannez
TD: Proximity Data and Power Transmission. ISSCC (2007)
Philippe Royannez, Hugh Mair, Franck Dahan, Mike Wagner, Mark Streeter, Laurent Bouetel, Joel Blasquez, H. Clasen, G. Semino, Julie Dong, D. Scott, B. Pitts, Claudine Raibaut, Uming Ko
A design platform for 90-nm leakage reduction techniques. DAC (2005)
Philippe Royannez, Amara Amara
A 1.0ns 64-bits GaAs Adder using Quad tree algorithm. Great Lakes Symposium on VLSI (1996)