Dinesh Pamunuwa

Publication Activity (10 Years)

Years Active: 2000-2024
Publications (10 Years): 4

Top Topics

Design Methodologies

Top Venues

IEEE Trans. Circuits Syst. I Regul. Pap.

Microprocess. Microsystems

Publications

Elliott Worsey, Qi Tang, Manu Bala Krishnan, Mukesh Kumar Kulsreshath, Dinesh Pamunuwa
Nanoelectromechanical analog-to-digital converter for low power and harsh environments. ISCAS (2024)
Tian Qin, Simon J. Bleiker, Sunil Rana, Frank Niklaus, Dinesh Pamunuwa
Performance Analysis of Nanoelectromechanical Relay-Based Field-Programmable Gate Arrays. IEEE Access 6 (2018)
Tian Qin, Sunil Rana, Dinesh Pamunuwa
Design Methodologies, Models and Tools for Very-Large-Scale Integration of NEM Relay-Based Circuits. ICCAD (2015)
Awet Yemane Weldezion, Matt Grange, Axel Jantsch, Hannu Tenhunen, Dinesh Pamunuwa
Zero-load predictive model for performance analysis in deflection routing NoCs. Microprocess. Microsystems 39 (8) (2015)
Sunil Rana, Tian Qin, Antonios Bazigos, Daniel Grogg, Michel Despont, Christopher Lawrence Ayala, Christoph Hagleitner, Adrian Mihai Ionescu, Roberto Canegallo, Dinesh Pamunuwa
Energy and Latency Optimization in NEM Relay-Based Digital Circuits. IEEE Trans. Circuits Syst. I Regul. Pap. (8) (2014)
Awet Yemane Weldezion, Matt Grange, Dinesh Pamunuwa, Axel Jantsch, Hannu Tenhunen
A scalable multi-dimensional NoC simulation model for diverse spatio-temporal traffic patterns. 3DIC (2013)
Sunil Rana, Tian Qin, Dinesh Pamunuwa, Daniel Grogg, Michel Despont, Yu Pu, Christoph Hagleitner
Modelling NEM relays for digital circuit applications. ISCAS (2013)
Dinesh Pamunuwa, Matthew Grange, Roshan Weerasekera, Axel Jantsch
3-D integration and the limits of silicon computation. VLSI-SoC (2011)
Matt Grange, Roshan Weerasekera, Dinesh Pamunuwa, Axel Jantsch, Awet Yemane Weldezion
Optimal network architectures for minimizing average distance in k-ary n-dimensional mesh networks. NOCS (2011)
Matthew Grange, Axel Jantsch, Roshan Weerasekera, Dinesh Pamunuwa
Modeling the computational efficiency of 2-D and 3-D silicon processors for early-chip planning. ICCAD (2011)
Roshan Weerasekera, Matt Grange, Dinesh Pamunuwa, Hannu Tenhunen
On signalling over Through-Silicon Via (TSV) interconnects in 3-D Integrated Circuits. DATE (2010)
Ci Lei, Dinesh Pamunuwa, Steven Bailey, Colin Lambert
Designing Reliable Digital Molecular Electronic Circuits. NanoNet (2009)
Ci Lei, Dinesh Pamunuwa, Steven Bailey, Colin Lambert
Design of Robust Molecular Electronic Circuits. ISCAS (2009)
Roshan Weerasekera, Dinesh Pamunuwa, Li-Rong Zheng, Hannu Tenhunen
Two-Dimensional and Three-Dimensional Integration of Heterogeneous Electronic Systems Under Cost, Performance, and Technological Constraints. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28 (8) (2009)
Awet Yemane Weldezion, Matt Grange, Dinesh Pamunuwa, Zhonghai Lu, Axel Jantsch, Roshan Weerasekera, Hannu Tenhunen
Scalability of network-on-chip communication architecture for 3-D meshes. NOCS (2009)
Matt Grange, Awet Yemane Weldezion, Dinesh Pamunuwa, Roshan Weerasekera, Zhonghai Lu, Axel Jantsch, Dave Shippen
Physical mapping and performance study of a multi-clock 3-Dimensional Network-on-Chip mesh. 3DIC (2009)
Roshan Weerasekera, Matt Grange, Dinesh Pamunuwa, Hannu Tenhunen, Li-Rong Zheng
Compact modelling of Through-Silicon Vias (TSVs) in three-dimensional (3-D) integrated circuits. 3DIC (2009)
Dinesh Pamunuwa
Memory Technology for Extended Large-Scale Integration in Future Electronics Applications. DATE (2008)
Ci Lei, Dinesh Pamunuwa, Steven Bailey, Colin Lambert
Application of Molecular Electronics Devices in Digital Circuit Design. NanoNet (2008)
Roshan Weerasekera, Dinesh Pamunuwa, Li-Rong Zheng, Hannu Tenhunen
Minimal-Power, Delay-Balanced Smart Repeaters for Global Interconnects in the Nanometer Regime. IEEE Trans. Very Large Scale Integr. Syst. 16 (5) (2008)
Roshan Weerasekera, Dinesh Pamunuwa, Li-Rong Zheng, Hannu Tenhunen
Delay-Balanced Smart Repeaters for On-Chip Global Signaling. VLSI Design (2007)
Roshan Weerasekera, Li-Rong Zheng, Dinesh Pamunuwa, Hannu Tenhunen
Extending systems-on-chip to the third dimension: performance, cost and technological tradeoffs. ICCAD (2007)
Roshan Weerasekera, Li-Rong Zheng, Dinesh Pamunuwa, Hannu Tenhunen
Early selection of system implementation choice among SoC, SoP and 3-D Integration. SoCC (2007)
Roshan Weerasekera, Dinesh Pamunuwa, Li-Rong Zheng, Hannu Tenhunen
Minimal-power, delay-balanced smart repeaters for interconnects in the nanometer regime. SLIP (2006)
Roshan Weerasekera, Li-Rong Zheng, Dinesh Pamunuwa, Hannu Tenhunen
Switching Sensitive Driver Circuit to Combat Dynamic Delay in On-Chip Buses. PATMOS (2005)
Dinesh Pamunuwa, Shauki Elassaad, Hannu Tenhunen
Modeling delay and noise in arbitrarily coupled RC trees. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24 (11) (2005)
Dinesh Pamunuwa, Johnny Öberg, Li-Rong Zheng, Mikael Millberg, Axel Jantsch, Hannu Tenhunen
A study on the implementation of 2-D mesh-based networks-on-chip in the nanometre regime. Integr. 38 (1) (2004)
Roshan Weerasekera, Li-Rong Zheng, Dinesh Pamunuwa, Hannu Tenhunen
Crosstalk immune interconnect driver design. SoC (2004)
Dinesh Pamunuwa, Shauki Elassaad
Closed form metrics to accurately model the response in general arbitrarily-coupled RC trees. ISCAS (4) (2003)
Dinesh Pamunuwa, Johnny Öberg, Li-Rong Zheng, Mikael Millberg, Axel Jantsch
Layout, Performance and Power Trade-Offs in Mesh-Based Network-on-Chip Architectures. VLSI-SOC (2003)
Dinesh Pamunuwa, Shauki Elassaad, Hannu Tenhunen
Analytic Modeling of Interconnects for Deep Sub-Micron Circuits. ICCAD (2003)
Jian Liu, Li-Rong Zheng, Dinesh Pamunuwa, Hannu Tenhunen
A global wire planning scheme for Network-on-Chip. ISCAS (4) (2003)
Dinesh Pamunuwa, Li-Rong Zheng, Hannu Tenhunen
Maximizing throughput over parallel wire structures in the deep submicrometer regime. IEEE Trans. Very Large Scale Integr. Syst. 11 (2) (2003)
Hannu Tenhunen, Dinesh Pamunuwa
On dynamic delay and repeater insertion. ISCAS (1) (2002)
Dinesh Pamunuwa, Li-Rong Zheng, Hannu Tenhunen
Optimising bandwidth over deep sub-micron interconnect. ISCAS (4) (2002)
Dinesh Pamunuwa, Hannu Tenhunen
On Dynamic Delay and Repeater Insertion in Distributed Capacitively Coupled Interconnects. ISQED (2002)
Dinesh Pamunuwa, Hannu Tenhunen
Repeater Insertion To Minimise Delay In Coupled Interconnects. VLSI Design (2001)
Dinesh Pamunuwa, Li-Rong Zheng, Hannu Tenhunen
Combating digital noise in high speed ULSI circuits using binary BCH encoding. ISCAS (2000)