Login / Signup
Layout, Performance and Power Trade-Offs in Mesh-Based Network-on-Chip Architectures.
Dinesh Pamunuwa
Johnny Öberg
Li-Rong Zheng
Mikael Millberg
Axel Jantsch
Published in:
VLSI-SOC (2003)
Keyphrases
</>
trade off
network on chip
power dissipation
power consumption
routing algorithm
interconnection networks
network simulator
multi processor
packet switched
real time
multistage
low power
signal processing
end to end