João Canas Ferreira

Publication Activity (10 Years)

Years Active: 1993-2021
Publications (10 Years): 27

Top Topics

Hardware Architecture

Genetic Algorithm

Top Venues

Microprocess. Microsystems

Publications

Tiago Santos, Nuno Paulino, João Bispo, João M. P. Cardoso, João Canas Ferreira
On the Performance Effect of Loop Trace Window Size on Scheduling for Configurable Coarse Grain Loop Accelerators. FPT (2021)
Nuno Paulino, João Bispo, João Canas Ferreira, João M. P. Cardoso
A Binary Translation Framework for Automated Hardware Generation. IEEE Micro 41 (4) (2021)
Luís Miguel Sousa, Nuno Miguel Cardanha Paulino, João Canas Ferreira, João Bispo
A Flexible HLS Hoeffding Tree Implementation for Runtime Learning on FPGA. CoRR (2021)
Nuno Paulino, João Canas Ferreira, João M. P. Cardoso
Optimizing OpenCL Code for Performance on FPGA: k-Means Case Study With Integer Data Sets. IEEE Access 8 (2020)
Fardin Derogarian, João Canas Ferreira, Vítor M. Grade Tavares, José Machado da Silva, Fernando J. Velez
A Multifunctional Integrated Circuit Router for Body Area Network Wearable Systems. IEEE/ACM Trans. Netw. 28 (5) (2020)
Nuno Paulino, João Canas Ferreira, João M. P. Cardoso
Improving Performance and Energy Consumption in Embedded Systems via Binary Acceleration: A Survey. ACM Comput. Surv. 53 (1) (2020)
Leonardo Alves Dias, João Canas Ferreira, Marcelo A. C. Fernandes
Parallel Implementation of K-Means Algorithm on FPGA. IEEE Access 8 (2020)
Guilherme Carvalho, João Canas Ferreira, Vítor Grade Tavares
Hardware architecture for integrate-and-fire signal reconstruction on FPGA. DCIS (2020)
Mário Lopes Ferreira, João Canas Ferreira
A Dynamically Reconfigurable Dual-Waveform Baseband Modulator for Flexible Wireless Communications. J. Signal Process. Syst. 92 (4) (2020)
Nuno Paulino, João Canas Ferreira, João Bispo, João M. P. Cardoso
Executing ARMv8 Loop Traces on Reconfigurable Accelerator via Binary Translation Framework. FPL (2020)
João Canas Ferreira, Francesca Palumbo
Preface to the Special Issue on Methods, Tools, and Architectures for Signal and Image Processing. J. Signal Process. Syst. 91 (7) (2019)
Nuno Miguel Cardanha Paulino, João Canas Ferreira, João M. P. Cardoso
Dynamic Partial Reconfiguration of Customized Single-Row Accelerators. IEEE Trans. Very Large Scale Integr. Syst. 27 (1) (2019)
Mário Lopes Ferreira, João Canas Ferreira, Michael Hübner
A Parallel-Pipelined OFDM Baseband Modulator with Dynamic Frequency Scaling for 5G Systems. ARC (2018)
Pedro Vieira dos Santos, José Carlos Alves, João Canas Ferreira
An FPGA array for cellular genetic algorithms: Application to the minimum energy broadcast problem. Microprocess. Microsystems 58 (2018)
Helder H. Avelar, João Canas Ferreira
Design and Evaluation of a Low Power CGRA Accelerator for Biomedical Signal Processing. DSD (2018)
Mário Lopes Ferreira, João Canas Ferreira
Flexible and Dynamically Reconfigurable FPGA-Based FS-FBMC Baseband Modulator. ISCAS (2018)
Fardin Derogarian, João Canas Ferreira, Vítor M. Grade Tavares
Analysis and Evaluation of anEnergy-Efficient Routing Protocol for WSNsCombining Source Routing and MinimumCost Forwarding. J. Mobile Multimedia 14 (4) (2018)
João Canas Ferreira, Paris Kitsos
MICPRO DSD 2015 special issue. Microprocess. Microsystems 52 (2017)
Benedikt Janßen, Fatih Korkmaz, Halil Derya, Michael Hübner, Mário Lopes Ferreira, João Canas Ferreira
Towards a type 0 hypervisor for dynamic reconfigurable systems. ReConFig (2017)
Miguel Carvalho, Mário Lopes Ferreira, João Canas Ferreira
FPGA-based implementation of a frequency spreading FBMC-OQAM baseband modulator. ICECS (2017)
Joao Lopes, Diogo Sousa, João Canas Ferreira
Evaluation of CGRA architecture for real-time processing of biological signals on wearable devices. ReConFig (2017)
Nuno Miguel Cardanha Paulino, João Canas Ferreira, João M. P. Cardoso
Generation of Customized Accelerators for Loop Pipelining of Binary Instruction Traces. IEEE Trans. Very Large Scale Integr. Syst. 25 (1) (2017)
Fardin Derogarian, João Canas Ferreira, Vítor Grade Tavares
A small fully digital open-loop clock and data recovery circuit for wired BANs. Int. J. Circuit Theory Appl. 44 (3) (2016)
Mário Lopes Ferreira, Amin Barahimi, João Canas Ferreira
Reconfigurable FPGA-Based FFT Processor for Cognitive Radio Applications. ARC (2016)
Pedro Miguel Santos, João Canas Ferreira, José Silva Matos
Scalable hardware architecture for disparity map computation and object location in real-time. J. Real Time Image Process. 11 (3) (2016)
Mário Lopes Ferreira, Amin Barahimi, João Canas Ferreira
Dynamically reconfigurable FFT processor for flexible OFDM baseband processing. DTIS (2016)
João Canas Ferreira, Jose Fonseca
An FPGA implementation of a long short-term memory neural network. ReConFig (2016)
Nuno Miguel Cardanha Paulino, João Canas Ferreira, João M. P. Cardoso
A Reconfigurable Architecture for Binary Acceleration of Loops with Memory Accesses. ACM Trans. Reconfigurable Technol. Syst. 7 (4) (2015)
Pedro Vieira dos Santos, José Carlos Alves, João Canas Ferreira
An FPGA Framework for Genetic Algorithms: Solving the Minimum Energy Broadcast Problem. DSD (2015)
Mário Lopes Ferreira, João Canas Ferreira
Reconfigurable NC-OFDM Processor for 5G Communications. EUC (2015)
Fardin Derogarian, João Canas Ferreira, Vítor M. Grade Tavares
A time synchronization circuit with sub-microsecond skew for multi-hop wired wearable networks. Microprocess. Microsystems 39 (8) (2015)
Nuno Miguel Cardanha Paulino, João Canas Ferreira, João Bispo, João M. P. Cardoso
Transparent acceleration of program execution using reconfigurable hardware. DATE (2015)
Nuno Miguel Cardanha Paulino, João Canas Ferreira, João Manuel Paiva Cardoso
Trace-Based Reconfigurable Acceleration with Data Cache and External Memory Support. ISPA (2014)
Fardin Derogarian, João Canas Ferreira, Vítor M. Grade Tavares
A Time Synchronization Circuit with an Average 4.6 ns One-Hop Skew for Wired Wearable Networks. DSD (2014)
Fardin Derogarian, João Canas Ferreira, Vítor Grade Tavares
Design and implementation of hybrid circuit/packet switching for wearable systems. ISIE (2014)
José Machado da Silva, Sylvie Renaud, João Canas Ferreira
Special issue of Microelectronics Journal on the Conference on Design of Circuits and Integrated Systems 2011 (DCIS 2011). Microelectron. J. 44 (10) (2013)
João Bispo, Nuno Miguel Cardanha Paulino, João M. P. Cardoso, João Canas Ferreira
Transparent Runtime Migration of Loop-Based Traces of Processor Instructions to Reconfigurable Processing Units. Int. J. Reconfigurable Comput. 2013 (2013)
Nuno Miguel Cardanha Paulino, João Canas Ferreira, João M. P. Cardoso
Architecture for Transparent Binary Acceleration of Loops with Memory Accesses. ARC (2013)
Filipe Sousa, Francis Anghinolfi, João Canas Ferreira
Register Transfer Level Workflow for Application and Evaluation of Soft Error Mitigation Techniques. DSD (2013)
João Bispo, Nuno Miguel Cardanha Paulino, João M. P. Cardoso, João Canas Ferreira
Transparent Trace-Based Binary Acceleration for Reconfigurable HW/SW Systems. IEEE Trans. Ind. Informatics 9 (3) (2013)
Pedro Vieira dos Santos, José Carlos Alves, João Canas Ferreira
A framework for hardware cellular genetic algorithms: An application to spectrum allocation in cognitive radio. FPL (2013)
Fardin Derogarian, João Canas Ferreira, Vítor M. Grade Tavares
Design and Implementation of a Circuit for Mesh Networks with Application in Body Area Networks. DSD (2012)
Miguel Lino Silva, João Canas Ferreira
Run-time generation of partial FPGA configurations for subword operations. Microprocess. Microsystems 36 (5) (2012)
Ali Azarian, João Canas Ferreira, Stephan Werner, Zlatko Petrov, João M. P. Cardoso, Michael Hübner
Analysis of error detection schemes: Toolchain support and hardware/software implications. AHS (2012)
Pedro Vieira dos Santos, José Carlos Alves, João Canas Ferreira
A scalable array for Cellular Genetic Algorithms: TSP as case study. ReConFig (2012)
Miguel Lino Silva, João Canas Ferreira
Run-time generation of partial FPGA configurations. J. Syst. Archit. 58 (1) (2012)
Andreina Zambrano, Fardin Derogarian, Ruben Dias, Maria José Abreu, André P. Catarino, Ana Maria Rocha, José Machado da Silva, João Canas Ferreira, Vítor Grade Tavares, Miguel Velhote Correia
A Wearable Sensor Network for Human Locomotion Data Capture. pHealth (2012)
João Bispo, Nuno Miguel Cardanha Paulino, João M. P. Cardoso, João Canas Ferreira
From Instruction Traces to Specialized Reconfigurable Arrays. ReConFig (2011)
Paulo Ferreira, João Canas Ferreira, José Carlos Alves
Erlang Inspired Hardware. FPL (2010)
Miguel Lino Silva, João Canas Ferreira
Creation of Partial FPGA Configurations at Run-Time. DSD (2010)
João G. P. Rodrigues, João Canas Ferreira
FPGA-based rectification of stereo images. DASIP (2010)
Miguel Lino Silva, João Canas Ferreira
Generation of partial FPGA configurations at run-time. FPL (2008)
Miguel Lino Silva, João Canas Ferreira
Generation of hardware modules for run-time reconfigurable hybrid CPU/FPGA systems. IET Comput. Digit. Tech. 1 (5) (2007)
M. L. Silva, João Canas Ferreira
Exploiting dynamic reconfiguration of platform FPGAs: implementation issues. IPDPS (2006)
Miguel Lino Silva, João Canas Ferreira
Support for partial run-time reconfiguration of platform FPGAs. J. Syst. Archit. 52 (12) (2006)
Miguel Lino Silva, João Canas Ferreira
Using a Tightly-Coupled Pipeline in Dynamically Reconfigurable Platform FPGAs. DSD (2005)
João Canas Ferreira, Miguel M. Silva
Run-Time Reconfiguration Support for FPGAs with Embedded CPUs: The Hardware Layer. IPDPS (2005)
João Canas Ferreira, José Silva Matos
A Development Support System for Applications That Use Dynamically Reconfigurable Hardware. FPL (2004)
José Carlos Alves, João Canas Ferreira, C. Albuquerque, José Fernando Oliveira, José Soeiro Ferreira, José Silva Matos
FAFNER-Accelerating Nesting Problems with FPGAs. FCCM (1999)
João Canas Ferreira, José Silva Matos
A Prototype System for Rapid Application Development using Dynamically Reconfigurable Hardware. FCCM (1998)
João Canas Ferreira, José Silva Matos
Mixed hardware/software applications on dynamically reconfigurable hardware. ICECS (1998)
João Canas Ferreira, José Carlos Alves, Célio Albuquerque, José Fernando Oliveira, José Soeiro Ferreira, José Silva Matos
Flexible hardware acceleration for nesting problems. ICECS (1998)
José Silva Matos, João Canas Ferreira, Ana C. Leão, José Machado da Silva
An Approach to Testability Improvement of Mixed-Signal Boards. ISCAS (1994)
José Silva Matos, João Canas Ferreira, Ana C. Leão, José Machado da Silva
Architecture of test support ICs for mixed-signal testing. VTS (1994)
José Silva Matos, Ana C. Leão, João Canas Ferreira
Control and Observation of Analog Nodes in Mixed-Signal Boards. ITC (1993)