Nuno Miguel Cardanha Paulino

Publication Activity (10 Years)

Years Active: 2011-2021
Publications (10 Years): 5

Top Topics

Reconfigurable Architecture

Reconfigurable Hardware

Program Execution

Top Venues

IEEE Trans. Very Large Scale Integr. Syst.

ACM Trans. Reconfigurable Technol. Syst.

Publications

Nuno Miguel Cardanha Paulino, Luís M. Pessoa, André Branquinho, Rafael Tavares, Igor Ferreira
Optimizing Packet Reception Rates for Low Duty-Cycle BLE Relay Nodes. CoRR (2021)
Pedro Filipe Silva, João Bispo, Nuno Miguel Cardanha Paulino
Building Beyond HLS: Graph Analysis and Others. CoRR (2021)
Luís Miguel Sousa, Nuno Miguel Cardanha Paulino, João Canas Ferreira, João Bispo
A Flexible HLS Hoeffding Tree Implementation for Runtime Learning on FPGA. CoRR (2021)
Nuno Miguel Cardanha Paulino, João Canas Ferreira, João M. P. Cardoso
Dynamic Partial Reconfiguration of Customized Single-Row Accelerators. IEEE Trans. Very Large Scale Integr. Syst. 27 (1) (2019)
Nuno Miguel Cardanha Paulino, João Canas Ferreira, João M. P. Cardoso
Generation of Customized Accelerators for Loop Pipelining of Binary Instruction Traces. IEEE Trans. Very Large Scale Integr. Syst. 25 (1) (2017)
Nuno Miguel Cardanha Paulino, João Canas Ferreira, João M. P. Cardoso
A Reconfigurable Architecture for Binary Acceleration of Loops with Memory Accesses. ACM Trans. Reconfigurable Technol. Syst. 7 (4) (2015)
Nuno Miguel Cardanha Paulino, João Canas Ferreira, João Bispo, João M. P. Cardoso
Transparent acceleration of program execution using reconfigurable hardware. DATE (2015)
Nuno Miguel Cardanha Paulino, João Canas Ferreira, João Manuel Paiva Cardoso
Trace-Based Reconfigurable Acceleration with Data Cache and External Memory Support. ISPA (2014)
João Bispo, Nuno Miguel Cardanha Paulino, João M. P. Cardoso, João Canas Ferreira
Transparent Runtime Migration of Loop-Based Traces of Processor Instructions to Reconfigurable Processing Units. Int. J. Reconfigurable Comput. 2013 (2013)
Nuno Miguel Cardanha Paulino, João Canas Ferreira, João M. P. Cardoso
Architecture for Transparent Binary Acceleration of Loops with Memory Accesses. ARC (2013)
João Bispo, Nuno Miguel Cardanha Paulino, João M. P. Cardoso, João Canas Ferreira
Transparent Trace-Based Binary Acceleration for Reconfigurable HW/SW Systems. IEEE Trans. Ind. Informatics 9 (3) (2013)
João Bispo, Nuno Miguel Cardanha Paulino, João M. P. Cardoso, João Canas Ferreira
From Instruction Traces to Specialized Reconfigurable Arrays. ReConFig (2011)