Run-time generation of partial FPGA configurations.

Miguel Lino Silva João Canas Ferreira

Published in: J. Syst. Archit. (2012)

Keyphrases

high speed
hardware implementation
generation process
real time
dedicated hardware
computer vision
real time image processing
hardware architecture
low cost
systolic array
partial information
signal processing
case study
website
image processing
social networks
information retrieval