José Silva Matos

Publication Activity (10 Years)

Years Active: 1992-2016
Publications (10 Years): 2

Top Topics

Object Location

Top Venues

Microprocess. Microsystems

J. Real Time Image Process.

Publications

Pedro Miguel Santos, João Canas Ferreira, José Silva Matos
Scalable hardware architecture for disparity map computation and object location in real-time. J. Real Time Image Process. 11 (3) (2016)
Francesco Leporati, José Silva Matos
MICPRO DSD 2014 special issue. Microprocess. Microsystems 39 (8) (2015)
José Silva Matos, Francesco Leporati
MICPRO DSD 2013 Special Issue. Microprocess. Microsystems 38 (8) (2014)
Francisco Duarte, José Machado da Silva, José Carlos Alves, G. A. Pinho, José Silva Matos
A processor for testing mixed-signal cores in System-on-Chip. DSD (2005)
João Canas Ferreira, José Silva Matos
A Development Support System for Applications That Use Dynamically Reconfigurable Hardware. FPL (2004)
Hélio Mendonça, José Machado da Silva, José Silva Matos
ADC testing using joint time-frequency analysis. Comput. Stand. Interfaces 23 (2) (2001)
José Machado da Silva, J. Soeiro Duarte, José Silva Matos
Mixed-Signal BIST Using Correlation and Reconfigurable Hardware. DATE (2000)
José Carlos Alves, João Canas Ferreira, C. Albuquerque, José Fernando Oliveira, José Soeiro Ferreira, José Silva Matos
FAFNER-Accelerating Nesting Problems with FPGAs. FCCM (1999)
João Canas Ferreira, José Silva Matos
A Prototype System for Rapid Application Development using Dynamically Reconfigurable Hardware. FCCM (1998)
José Carlos Alves, José Silva Matos
RVC - A Reconfigurable Coprocessor for Vector Processing Applications. FCCM (1998)
João Canas Ferreira, José Silva Matos
Mixed hardware/software applications on dynamically reconfigurable hardware. ICECS (1998)
José Silva Matos
Computer Organisation, Programming and Benchmarking - Introduction. VECPAR (1998)
João Canas Ferreira, José Carlos Alves, Célio Albuquerque, José Fernando Oliveira, José Soeiro Ferreira, José Silva Matos
Flexible hardware acceleration for nesting problems. ICECS (1998)
José Silva Matos, José Machado da Silva
Mixed-Signal Board Level DfT Techniques Using IEEE P1149.4. ICECS (1998)
José Carlos Alves, André T. Puga, Luís Corte-Real, José Silva Matos
A vector architecture for higher-order moments estimation. ICASSP (1997)
José Machado da Silva, Ana C. Leão, José Silva Matos, José Carlos Alves
Implementation of Mixed Current/Voltage Testing Using the IEEE P1149.4 Infrastructure. ITC (1997)
José Carlos Alves, André T. Puga, Luís Corte-Real, José Silva Matos
ProHos-1 - A Vector Processor for the Efficient Estimation of Higher-Order Moments. VECPAR (1996)
José Machado da Silva, José Silva Matos, Ian M. Bell, Gaynor E. Taylor
Mixed current/voltage observation towards effective testing of analog and mixed-signal circuits. J. Electron. Test. 9 (1-2) (1996)
José Machado da Silva, José Silva Matos
Evaluation of iDD/vOUT Cross-Correlation for Mixed Current/Voltage Testing of Analogue and Mixed-Signal Circuits. ED&TC (1996)
José Silva Matos, João Canas Ferreira, Ana C. Leão, José Machado da Silva
An Approach to Testability Improvement of Mixed-Signal Boards. ISCAS (1994)
José Silva Matos, João Canas Ferreira, Ana C. Leão, José Machado da Silva
Architecture of test support ICs for mixed-signal testing. VTS (1994)
José Silva Matos, Ana C. Leão, João Canas Ferreira
Control and Observation of Analog Nodes in Mixed-Signal Boards. ITC (1993)
José M. M. Ferreira, Filipe S. Pinto, José Silva Matos
A Boundary Scan Test Controller for Hierarchical BIST. ITC (1992)