Hortensia Mecha

Publication Activity (10 Years)

Years Active: 1994-2023
Publications (10 Years): 8

Top Topics

Hardware Implementation

Software Components

Power Consumption

Top Venues

IET Comput. Digit. Tech.

Microprocess. Microsystems

Publications

Juan Carlos Fabero, Golnaz Korkian, Francisco J. Franco, Guillaume Hubert, Hortensia Mecha, Manon Letiche, Juan Antonio Clemente
SEE sensitivity of a COTS 28-nm SRAM-based FPGA under thermal neutrons and different incident angles. Microprocess. Microsystems 96 (2023)
Golnaz Korkian, Daniel León, Francisco J. Franco, Juan Carlos Fabero, Manon Letiche, Yolanda Morilla, Pedro Martin-Holgado, Helmut Puchner, Hortensia Mecha, Juan Antonio Clemente
Single Event Upsets Under Proton, Thermal, and Fast Neutron Irradiation in Emerging Nonvolatile Memories. IEEE Access 10 (2022)
Mohammadreza Rezaei, Francisco J. Franco, Juan Carlos Fabero, Hortensia Mecha, Helmut Puchner, Juan Antonio Clemente
Impact of DVS on Power Consumption and SEE Sensitivity of COTS Volatile SRAMs. LATS (2021)
Juan C. Fabero, Golnaz Korkian, Francisco J. Franco, Hortensia Mecha, Manon Letiche, Juan Antonio Clemente
Thermal Neutron-induced SEUs on a COTS 28-nm SRAM-based FPGA under Different Incident Angles. LATS (2021)
Adrián Alcolea Morena, Javier Olivito, Javier Resano, Hortensia Mecha
Analysis of a Pipelined Architecture for Sparse DNNs on Embedded Systems. IEEE Trans. Very Large Scale Integr. Syst. 28 (9) (2020)
Javier Olivito, Felipe Serrano, Juan Antonio Clemente, Hortensia Mecha, Javier Resano
Analysis of the reconfiguration latency and energy overheads for a Xilinx Virtex-5 field-programmable gate array. IET Comput. Digit. Tech. 12 (4) (2018)
Juan Antonio Clemente, Wassim Mansour, Rafic Ayoubi, Felipe Serrano, Hortensia Mecha, Haissam Ziade, Wassim El Falou, Raoul Velazco
Hardware implementation of a fault-tolerant Hopfield Neural Network on FPGAs. Neurocomputing 171 (2016)
Marcos Sanchez-Elez, Inmaculada Pardines, Felipe Serrano, Hortensia Mecha
Radiation-hardened DSP configurations for implementing arithmetic functions on FPGA. DATE (2016)
Sara Román Navarro, Hortensia Mecha, Daniel Mozos
A Constant Complexity Allocation Algorithm for Reconfigurable Systems Management Adapted to Heterogeneous Workload Profiles. ERSA (2010)
Jose Antonio Valero, Julio Septién, Daniel Mozos, Hortensia Mecha
3D FPGA resource management and fragmentation metric for hardware multitasking. IPDPS (2009)
Jesús Tabero, Julio Septién, Hortensia Mecha, Daniel Mozos
Allocation heuristics and defragmentation measures for reconfigurable systems management. Integr. 41 (2) (2008)
Julio Septién, Daniel Mozos, Hortensia Mecha, Jesús Tabero, Miguel Angel García de Dios
Perimeter quadrature-based metric for estimating FPGA fragmentation in 2D HW multitasking. IPDPS (2008)
Angel Luis González Bravo, Hortensia Mecha, Julio Septién, Sara Román Navarro, Daniel Mozos
Synthesis of relocatable tasks and implementation of a task communication bus in a general purpose Hw system. ERSA (2008)
Laura Sánchez, Julio Septién, Daniel Mozos, Hortensia Mecha, Angel Luis González Bravo
FPGA Resource Management Using Internal RAM as Aata Cache. ERSA (2008)
S. Roman, Hortensia Mecha, Daniel Mozos, Julio Septién
Constant complexity scheduling for hardware multitasking in two dimensional reconfigurable field-programmable gate arrays. IET Comput. Digit. Tech. 2 (6) (2008)
Jose Antonio Valero, Julio Septién, Daniel Mozos, Hortensia Mecha, Angel Luis González Bravo
Resource Management for Hw Multitasking in Three Dimensional FPGAs. ERSA (2008)
Julio Septién, Hortensia Mecha, Daniel Mozos, Jesús Tabero
2D defragmentation heuristics for hardware multitasking on reconfigurable devices. IPDPS (2006)
Sara Román Navarro, Hortensia Mecha, Daniel Mozos, Julio Septién
Partition Based Dynamic 2D HW Multitasking Management. DSD (2006)
Jesús Tabero, Julio Septién, Hortensia Mecha, Daniel Mozos
Task placement heuristic based on 3D-adjacency and look-ahead in reconfigurable systems. ASP-DAC (2006)
Sara Román Navarro, Julio Septién, Hortensia Mecha, Daniel Mozos
Constant Complexity Management of 2D HW Multitasking in Run-Time Reconfigurable FPGAs. ARC (2006)
Jesús Tabero, Julio Septién, Hortensia Mecha, Daniel Mozos
A Low Fragmentation Heuristic for Task Placement in 2D RTR HW Management. FPL (2004)
Javier Resano, Daniel Mozos, Elena Pérez-Miñana, Hortensia Mecha, Julio Septién
A Hardware/Software Partitioning and Scheduling Approach for Embedded Systems with Low-Power and High Performance Requirements. PATMOS (2003)
Javier Resano, M. Elena Pérez, Daniel Mozos, Hortensia Mecha, Julio Septién
Analyzing communication overheads during hardware/software partitioning. Microelectron. J. 34 (11) (2003)
Katzalin Olcoz, Francisco Tirado, Hortensia Mecha
Unified data path allocation and BIST intrusion. Integr. 28 (1) (1999)
Juan Antonio Maestro, Daniel Mozos, Hortensia Mecha
A Macroscopic Time and Cost Estimation Model Allowing Task Parallelism and Hardware Sharing for the Codesign Partitioning Process. DATE (1998)
Hortensia Mecha, Milagros Fernández
Interconnection Delay and Clock Cycle Selection in High Level Synthesis. VLSI Design (1997)
R. Moreno, Román Hermida, Milagros Fernández, Hortensia Mecha
A unified approach for scheduling and allocation. Integr. 23 (1) (1997)
Hortensia Mecha, Milagros Fernández, Francisco Tirado, Julio Septién, D. Motes, Katzalin Olcoz
A method for area estimation of data-path in high level synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15 (2) (1996)
Hortensia Mecha, Milagros Fernández, Román Hermida, Daniel Mozos, Katzalin Olcoz
Clock cycle estimation based on dead time and control unit area minimization. Microprocess. Microprogramming 40 (10-12) (1994)