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Analysis of the reconfiguration latency and energy overheads for a Xilinx Virtex-5 field-programmable gate array.
Javier Olivito
Felipe Serrano
Juan Antonio Clemente
Hortensia Mecha
Javier Resano
Published in:
IET Comput. Digit. Tech. (2018)
Keyphrases
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field programmable gate array
hardware implementation
neural network
artificial intelligence
response time
image processing algorithms
computer vision
high speed
hardware architecture
programmable logic
xilinx virtex