Hiromu Fujioka

Publication Activity (10 Years)

Years Active: 1996-2007
Publications (10 Years): 0

Publications

Koji Nakamae, Masaki Chikahisa, Hiromu Fujioka
Estimation of electron probe profile from SEM image through wavelet multiresolution analysis for inline SEM inspection. Image Vis. Comput. 25 (7) (2007)
Yasuyuki Yamada, Koji Nakamae, Hiromu Fujioka
Image deblurring by the combined use of a super-resolution technique and inverse filtering. Computational Imaging (2006)
Katsuyoshi Miura, Tomoyuki Kobatake, Koji Nakamae, Hiromu Fujioka
A low energy FIB processing, repair, and test system. Microelectron. Reliab. 43 (9-11) (2003)
Youhei Zenda, Koji Nakamae, Hiromu Fujioka
Cost Optimum Embedded DRAM Design by Yield Analysis. MTDT (2003)
Katsuyoshi Miura, Koji Nakamae, Hiromu Fujioka
CAD navigation system, for backside waveform probing of CMOS devices. Microelectron. Reliab. 42 (9-11) (2002)
Katsuyoshi Miura, Koji Nakamae, Hiromu Fujioka
Development of an EB/FIB Integrated Test System. Microelectron. Reliab. 41 (9-10) (2001)
Koji Nakamae, Takashi Ishimura, Hiromu Fujioka
EB tester fault localization algorithm for combinational circuits by utilizing fault simulation and test pattern sequence for EB tester. Systems and Computers in Japan 31 (8) (2000)
Katsuyoshi Miura, Koji Nakamae, Hiromu Fujioka
Intelligent EB Test System for Automatic VLSI Fault Tracing. Asian Test Symposium (1999)
Koji Nakamae, Shinji Yokoyama, Atsushi Onishi, Hiromu Fujioka
Knowledge-based circuit recognition from standard-cell design CMOS VLSI optical microscope images. Systems and Computers in Japan 29 (4) (1998)
Katsuyoshi Miura, Koji Nakamae, Hiromu Fujioka
Hierarchical VLSI Fault Tracing by Successive Circuit Extraction from CAD Layout Data in the CAD-Linked EB Test System. J. Electron. Test. 10 (3) (1997)
Katsuyoshi Miura, Kohei Nakata, Koji Nakamae, Hiromu Fujioka
Automatic EB Fault Tracing System by Successive Circuit Extraction from VLSI CAD Layout Data. Asian Test Symposium (1997)
Katsuyoshi Miura, Koji Nakamae, Hiromu Fujioka
Hierarchical fault tracing for VLSI sequential circuits from CAD layout data in the CAD-linked EB test system. ASP-DAC (1997)
Hiromu Fujioka, Koji Nakamae, Akio Higashi
Effects of Multi-Product, Small-Sized Production of LSIs Packaged in Various Packages on the Final Test Process Efficiency and Cost. ITC (1996)
Koji Nakamae, Homare Sakamoto, Hiromu Fujioka
How ATE Planning Affects LSI Manufacturing Cost. IEEE Des. Test Comput. 13 (4) (1996)