Chiu-sing Choy

Publication Activity (10 Years)

Years Active: 1994-2018
Publications (10 Years): 6

Top Topics

Abstraction Levels

Selecting Relevant Features

Top Venues

Publications

Weiwei Shi, An Pan, Shi Yu, Chiu-sing Choy
A Subthreshold Baseband Processor Core Design With Custom Modules and Cells for Passive RFID Tags. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37 (1) (2018)
Zhou Fang, Howan Leung, Chiu-sing Choy
Spatial temporal GRU convnets for vision-based real time epileptic seizure detection. ISBI (2018)
Hongda Wang, Weiwei Shi, Chiu-sing Choy
Integrating channel selection and feature selection in a real time epileptic seizure detection system. EMBC (2017)
Lie Xu, Chiu-sing Choy, Yi-Wen Li
Deep sparse rectifier neural networks for speech denoising. IWAENC (2016)
Hongda Wang, Chiu-sing Choy
Automatic seizure detection using correlation integral with nonlinear adaptive denoising and Kalman filter. EMBC (2016)
Weiwei Shi, Chiu-sing Choy
A 0.4V 320Mb/s 28.7µW 1024-bit configurable multiplier for subthreshold SOC encryption. SoCC (2016)
Hao Wang, Xian Tang, Chiu-sing Choy, Ka Nang Leung, Kong-Pang Pun
A 5.4-mW 180-cm Transmission Distance 2.5-Mb/s Advanced Techniques-Based Novel Intrabody Communication Receiver Analog Front End. IEEE Trans. Very Large Scale Integr. Syst. 23 (12) (2015)
Weiwei Shi, Linqing Fu, Chiu-sing Choy
Subthreshold passive RFID tag's baseband processor core design with custom modules and cells. ICECS (2015)
Ho Chuen Jackson Yeung, Evangeline F. Y. Young, Chiu-sing Choy
Reducing pin count on cross-referencing Digital Microfluidic Biochip. ISCAS (2014)
Jianfeng Wang, Chiu-sing Choy, Tak Lon Chao, Ko-Chun Kit, Kong-Pang Pun, Wanli Ouyang, Xiao-Gang Wang
Simplifying HOG arithmetic for speedy hardware realization. APCCAS (2014)
Ke Xu, Min Zhang, Chiu-sing Choy
Design a Low-Power H.264/AVC Baseline Decoder at All Abstraction Levels - A Showcase. J. Signal Process. Syst. 67 (3) (2012)
Pui-wai Chan, Chiu-sing Choy
Performance evaluation of OFDM de-modulator with various multiplier architectures for UWB system. APCCAS (2010)
Ka Nang Leung, Chiu-sing Choy, Kong-Pang Pun, Lincoln Lai Kan Leung, Jianping Guo, Yuen Sum Ng, Chi Fat Chan, Weiwei Shi, Yang Hong, Marco Ho, Ki-Leung Mak, Yanqing Ai
RF Module Design of Passive UHF RFID Tag Implemented in CMOS 90-nm Technology. J. Low Power Electron. 6 (1) (2010)
Ling Xin, Chiu-sing Choy
A low-latency NoC router with lookahead bypass. ISCAS (2010)
Yang Hong, Chi Fat Chan, Jianping Guo, Yuen Sum Ng, Weiwei Shi, Lincoln Lai Kan Leung, Ka Nang Leung, Chiu-sing Choy, Kong-Pang Pun
Design of passive UHF RFID tag in 130nm CMOS technology. APCCAS (2008)
Ke Xu, Chiu-sing Choy
A Five-Stage Pipeline, 204 Cycles/MB, Single-Port SRAM-Based Deblocking Filter for H.264/AVC. IEEE Trans. Circuits Syst. Video Technol. 18 (3) (2008)
Min Zhang, Chiu-sing Choy
Low-Cost VC Allocator Design for Virtual Channel Wormhole Routers in Networks-on-Chip. NOCS (2008)
Ke Xu, Chiu-sing Choy
Low-power H.264/AVC baseline decoder for portable applications. ISLPED (2007)
Ke Xu, Chiu-sing Choy, Cheong-fat Chan, Kong-Pang Pun
Power-Efficient VLSI Realization of a Complex FSM for H.264/AVC Bitstream Parsing. IEEE Trans. Circuits Syst. II Express Briefs (11) (2007)
Pui-Tak So, Cheong-fat Chan, Chiu-sing Choy, Kong-Pang Pun
Ramp voltage supply using adiabatic charging principle. ISCAS (3) (2005)
Wei Han, Cheong-fat Chan, Chiu-sing Choy, Kong-Pang Pun
A speech recognizer with selectable model parameters. ISCAS (6) (2005)
Chi-Leung San, Chiu-sing Choy, Pak-Kee Chan, Cheong-fat Chan, Kong-Pang Pun
Realization of card-centric framework: a card-centric computer [smart cards]. ISCAS (5) (2005)
Chun-Pong Yu, Chiu-sing Choy, Hao Min, Cheong-fat Chan, Kong-Pang Pun
A low power asynchronous Java processor for contactless smart card. ASP-DAC (2004)
Jing-ling Yang, Chiu-sing Choy, Cheong-fat Chan, Kong-Pang Pun
A high-efficiency strongly self-checking asynchronous datapath. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23 (10) (2004)
Hongwei Wang, Cheong-fat Chan, Chiu-sing Choy
High Speed Curve Interpolating D/A Converter. J. VLSI Signal Process. 38 (1) (2004)
Wing-Kin Chan, Chiu-sing Choy, Cheong-fat Chan, Kong-Pang Pun
An asynchronous SOVA decoder for wireless communication application. ISCAS (2) (2004)
Wang Tung Cheng, Kong-Pang Pun, Cheong-fat Chan, Chiu-sing Choy
An IF-sampling SC complex lowpass Sigma Delta modulator with high image rejection by capacitor sharing. ISCAS (1) (2004)
Junhua Shen, Kong-Pang Pun, Chiu-sing Choy, Cheong-fat Chan
An IF input continuous-time sigma-delta analog-digital converter with high image rejection. ICECS (2004)
Kong-Pang Pun, Chiu-sing Choy, Cheong-fat Chan, José Epifânio da Franca
An I/Q mismatch-free switched-capacitor complex sigma-delta Modulator. IEEE Trans. Circuits Syst. II Express Briefs (5) (2004)
Pak-Kee Chan, Chiu-sing Choy, Cheong-fat Chan, Kong-Pang Pun
Preparing smartcard for the future: from passive to active. IEEE Trans. Consumer Electron. 50 (1) (2004)
Pak-Keung Leung, Chiu-sing Choy, Cheong-fat Chan, Kong-Pang Pun
) ALU for elliptic curve crypto-processor. ISCAS (5) (2003)
Wei Han, Kwok-Wai Hon, Cheong-fat Chan, Tan Lee, Chiu-sing Choy, Kong-Pang Pun, Pak-Chung Ching
An HMM-based speech recognition IC. ISCAS (2) (2003)
W. K. Yeung, Cheong-fat Chan, Chiu-sing Choy, Kong-Pang Pun
Clock recovery circuit with adiabatic technology (quasi-static CMOS logic). ISCAS (2) (2003)
Hongwei Wang, Cheong-fat Chan, Chiu-sing Choy
A 12-bit 80 Ms/s 110 mW floating analog-to-digital converter. ISCAS (3) (2002)
Kong-Pang Pun, Chiu-sing Choy, Cheong-fat Chan, José E. Franca
A quadrature IF mixer with high image rejection for continuous-time complex Sigma-Delta modulators. ISCAS (4) (2002)
Kin-Pui Ho, Cheong-fat Chan, Chiu-sing Choy, Kong-Pang Pun
A CMOS current feedback operational amplifier with active current mode compensation. ISCAS (1) (2002)
Pui-Lam Siu, Chiu-sing Choy, Jan Butas, Cheong-fat Chan
A low power asynchronous DES. ISCAS (4) (2001)
Chi-Wai Lee, Chiu-sing Choy, Jan Butas, Cheong-fat Chan
A pipelined dataflow small micro-coded asynchronous processor and its application to DCT. ISCAS (4) (2001)
Tin-Y. Tang, Chiu-sing Choy, Pui-Lam Siu, Cheong-fat Chan
Design of self-timed asynchronous Booth's multiplier. ASP-DAC (2000)
Tin-Yau Tang, Chiu-sing Choy, Jan Butas, Cheong-fat Chan
An ALU design using a novel asynchronous pipeline architecture. ISCAS (2000)
Hongwei Wang, Cheong-fat Chan, Chiu-sing Choy
High speed CMOS digital-to-analog converter with linear interpolator. IEEE Trans. Consumer Electron. 46 (4) (2000)
Hongwei Wang, Cheong-fat Chan, Chiu-sing Choy
CMOS high speed interpolators based on parallel architecture. IEEE Trans. Consumer Electron. 46 (2) (2000)
Chiu-sing Choy, Tsz-Shing Cheung, Kam-Keung Wong
Incremental layout placement modification algorithms. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15 (4) (1996)
Chiu-sing Choy, Cheong-fat Chan, M. H. Ku
A Feedback Control Circuit Design Technique to Suppress Power Noise in High Speed Output Driver. ISCAS (1995)
W. Y. Lo, Chiu-sing Choy, Cheong-fat Chan
Hardware emulation board based on FPGAs and programmable interconnections. RSP (1994)