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Design of passive UHF RFID tag in 130nm CMOS technology.
Yang Hong
Chi Fat Chan
Jianping Guo
Yuen Sum Ng
Weiwei Shi
Lincoln Lai Kan Leung
Ka Nang Leung
Chiu-sing Choy
Kong-Pang Pun
Published in:
APCCAS (2008)
Keyphrases
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cmos technology
rfid tags
low power
power consumption
low cost
low voltage
power dissipation
spl times
low power consumption
rfid reader
lightweight
design process
parallel processing
authentication protocol
single chip
mixed signal