CMOS high speed interpolators based on parallel architecture.

Hongwei Wang Cheong-fat Chan Chiu-sing Choy

Published in: IEEE Trans. Consumer Electron. (2000)

Keyphrases

high speed
parallel architecture
low power
parallel processing
hardware implementation
systolic array
shared memory
high level synthesis
real time
frame rate
parallel implementation
synthetic aperture sonar
distributed memory
focal plane
low cost
design process
higher order
image processing