Clock recovery circuit with adiabatic technology (quasi-static CMOS logic).

W. K. Yeung Cheong-fat Chan Chiu-sing Choy Kong-Pang Pun

Published in: ISCAS (2) (2003)

Keyphrases

high speed
quasi static
delay insensitive
cmos technology
power consumption
low power
circuit design
chip design
analog vlsi
nm technology
low voltage
silicon on insulator
metal oxide semiconductor
asynchronous circuits
duty cycle
multiresolution
image processing