Andrzej Hlawiczka

Publication Activity (10 Years)

Years Active: 1978-2010
Publications (10 Years): 0

Publications

Tomasz Garbolino, Krzysztof Gucwa, Andrzej Hlawiczka
Reduced-size signature-based diagnostic dictionary for interconnection testing. PDeS (2010)
Tomasz Garbolino, Krzysztof Gucwa, Andrzej Hlawiczka
How to reduce size of a signature-based diagnostic dictionary used for testing of connections. DDECS (2010)
Tomasz Rudnicki, Tomasz Garbolino, Krzysztof Gucwa, Andrzej Hlawiczka
Effective BIST for crosstalk faults in interconnects. DDECS (2009)
Andrzej Hlawiczka, Krzysztof Gucwa, Tomasz Garbolino, Michal Kopec
Interconnect Faults Identification and Localization Using Modified Ring LFSRs. DDECS (2008)
Tomasz Rudnicki, Andrzej Hlawiczka
Test Pattern Generator for Delay Faults. DDECS (2007)
Tomasz Garbolino, Krzysztof Gucwa, Michal Kopec, Andrzej Hlawiczka
Avoiding Crosstalk Influence on Interconnect Delay Fault Testing. DDECS (2007)
Tomasz Garbolino, Michal Kopec, Krzysztof Gucwa, Andrzej Hlawiczka
Detection, Localisation and Identification of Interconnection Faults Using MISR Compactor. DDECS (2006)
Michal Kopec, Tomasz Garbolino, Krzysztof Gucwa, Andrzej Hlawiczka
Test-per-Clock Detection, Localization and Identification of Interconnect Faults. ETS (2006)
Ondrej Novák, Zdenek Plíva, Jiri Nosek, Andrzej Hlawiczka, Tomasz Garbolino, Krzysztof Gucwa
Test-Per-Clock Logic BIST with Semi-Deterministic Test Patterns and Zero-Aliasing Compactor. J. Electron. Test. 20 (1) (2004)
Tomasz Garbolino, Andrzej Hlawiczka
Efficient test pattern generators based on specific cellular automata structures. Microelectron. Reliab. 42 (6) (2002)
Andrzej Hlawiczka, Michal Kopec
Dependable testing of compactor MISR: an imperceptible problem? ETW (2002)
Andrzej Hlawiczka, Michal Kopec
Design and testing of fast and cost effective serial seeding TPGs based on one-dimensional linear hybrid cellular automata. Asian Test Symposium (2000)
Tomasz Garbolino, Andrzej Hlawiczka, Adam Kristof
Fast and low-area TPGs based on T-type flip-flops can be easily integrated to the scan path. ETW (2000)
Tomasz Garbolino, Andrzej Hlawiczka
A New LFSR with D and T Flip-Flops as an Effective Test Pattern Generator for VLSI Circuits. EDCC (1999)
Dariusz Badura, Andrzej Hlawiczka
Low Cost Bist for Edac Circuits. Asian Test Symposium (1997)
Andrzej Hlawiczka, Michael Gössel, Egor S. Sogomonyan
A linear code-preserving signature analyzer COPMISR. VTS (1997)
Andrzej Hlawiczka, Jacek Binda
Optimized Synthesis of Self-Testable Finite State Machines (FSM) Using BIST-PST Structures in Altera Structures. FPL (1994)
Andrzej Hlawiczka
Parallel Signature Analyzers Using Hybrid Design of Their Linear Feedbacks. IEEE Trans. Computers 41 (12) (1992)
Andrzej Hlawiczka
Signature Analysis Testing with Bottom-Top Exclusive Or Type MISR. Fehlertolerierende Rechensysteme (1989)
Andrzej Hlawiczka, Dariusz Badura
Universal Test Controller Chip for Board Self Test. Fehlertolerierende Rechensysteme (1987)
Andrzej Hlawiczka
Compression of Three-State Data Serial Streams by Means of a Parallel LFSR Signature Analyzer. IEEE Trans. Computers 35 (8) (1986)
Andrzej Hlawiczka
Compression of multiple-valued data serial streams by means of parallel LFSR signature analyzer. Fehlertolerierende Rechensysteme (1984)
Andrzej Hlawiczka
Comments on "Procedures for Eliminating Static and Dynamic-Hazards in Test Generation". IEEE Trans. Computers 27 (2) (1978)