Tomasz Garbolino

Publication Activity (10 Years)

Years Active: 1999-2014
Publications (10 Years): 0

Top Topics

Fault Detection

Built In Self Test

Top Venues

Publications

Tomasz Garbolino
Designing of Test Pattern Generators for stimulation of crosstalk faults in bus-type connections. DDECS (2014)
Gregor Papa, Tomasz Garbolino
Optimal on-line built-in self-test structure for system-reliability improvement. IEEE Congress on Evolutionary Computation (2011)
Tomasz Garbolino, Krzysztof Gucwa, Andrzej Hlawiczka
Reduced-size signature-based diagnostic dictionary for interconnection testing. PDeS (2010)
Tomasz Garbolino, Gregor Papa
Genetic algorithm for test pattern generator design - Automatic evolution of circuits. Appl. Intell. 32 (2) (2010)
Tomasz Garbolino, Krzysztof Gucwa, Andrzej Hlawiczka
How to reduce size of a signature-based diagnostic dictionary used for testing of connections. DDECS (2010)
Tomasz Rudnicki, Tomasz Garbolino, Krzysztof Gucwa, Andrzej Hlawiczka
Effective BIST for crosstalk faults in interconnects. DDECS (2009)
Tomasz Garbolino, Gregor Papa
Test Pattern Generator Design Optimization Based on Genetic Algorithm. IEA/AIE (2008)
Andrzej Hlawiczka, Krzysztof Gucwa, Tomasz Garbolino, Michal Kopec
Interconnect Faults Identification and Localization Using Modified Ring LFSRs. DDECS (2008)
Gregor Papa, Tomasz Garbolino, Franc Novak
Deterministic Test Pattern Generator Design. EvoWorkshops (2008)
Tomasz Garbolino, Krzysztof Gucwa, Michal Kopec, Andrzej Hlawiczka
Avoiding Crosstalk Influence on Interconnect Delay Fault Testing. DDECS (2007)
Tomasz Garbolino, Michal Kopec, Krzysztof Gucwa, Andrzej Hlawiczka
Detection, Localisation and Identification of Interconnection Faults Using MISR Compactor. DDECS (2006)
Michal Kopec, Tomasz Garbolino, Krzysztof Gucwa, Andrzej Hlawiczka
Test-per-Clock Detection, Localization and Identification of Interconnect Faults. ETS (2006)
Ondrej Novák, Zdenek Plíva, Jiri Nosek, Andrzej Hlawiczka, Tomasz Garbolino, Krzysztof Gucwa
Test-Per-Clock Logic BIST with Semi-Deterministic Test Patterns and Zero-Aliasing Compactor. J. Electron. Test. 20 (1) (2004)
Tomasz Garbolino, Andrzej Hlawiczka
Efficient test pattern generators based on specific cellular automata structures. Microelectron. Reliab. 42 (6) (2002)
Tomasz Garbolino, Andrzej Hlawiczka, Adam Kristof
Fast and low-area TPGs based on T-type flip-flops can be easily integrated to the scan path. ETW (2000)
Tomasz Garbolino, Andrzej Hlawiczka
A New LFSR with D and T Flip-Flops as an Effective Test Pattern Generator for VLSI Circuits. EDCC (1999)