Nanosheet-based Complementary Field-Effect Transistors (CFETs) at 48nm Gate Pitch, and Middle Dielectric Isolation to enable CFET Inner Spacer Formation and Multi-Vt Patterning.
Hans MertensM. HosseiniThomas ChiarellaD. ZhouS. WangG. MannaertE. DupuyD. RadisicZ. TaoY. OnikiAndriy HikavyyR. RosseelA. MingardiS. ChoudhuryP. Puttarame GowdaF. SebaaiA. PeterKevin VandersmissenJ. P. SoulieAn De KeersgieterL. Petersen Barbosa LimaC. CavalcanteD. BatukG. T. MartinezJ. GeypenF. SeidelK. PaulussenP. FaviaJürgen BömmelsRoger LooP. WongA. Sepulveda MarquezB. T. ChanJérôme MitardS. SubramanianS. DemuynckE. Dentoni LittaN. HoriguchiS. SamavedamS. BiesemansPublished in: VLSI Technology and Circuits (2023)
Keyphrases
- field effect transistors
- high density
- schottky barrier
- steady state
- gate dielectrics
- metal oxide semiconductor
- mathematical analysis
- transmission line
- semiconductor devices
- gate insulator
- integrated circuit
- leakage current
- real time
- silicon dioxide
- databases
- markov chain
- information systems
- chemical vapor deposition
- neural network
- parallel processing
- data center
- genetic algorithm
- nm technology