Tatsuya Hirose

Publication Activity (10 Years)

Years Active: 2002-2013
Publications (10 Years): 0

Top Topics

Perceptual Information

Top Venues

J. Robotics Mechatronics

Publications

Hidekazu Suzuki, Katsuhiro Naito, Kazuma Kamienoo, Tatsuya Hirose, Akira Watanabe
NTMobile: new end-to-end communication architecture in IPv4 and IPv6 networks. MobiCom (2013)
Tatsuya Hirose, Tadahiro Taniguchi
Abstraction Multimodal Low-Dimensional Representation from High-Dimensional Posture Information and Visual Images. J. Robotics Mechatronics 25 (1) (2013)
Ning Li, Keigo Bunsen, Naoki Takayama, Qinghong Bu, Toshihide Suzuki, Masaru Sato, Yoichi Kawano, Tatsuya Hirose, Kenichi Okada, Akira Matsuzawa
A 24 dB Gain 51-68 GHz Common Source Low Noise Amplifier Using Asymmetric-Layout Transistors. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (2) (2012)
Ning Li, Keigo Bunsen, Naoki Takayama, Qinghong Bu, Toshihide Suzuki, Masaru Sato, Tatsuya Hirose, Kenichi Okada, Akira Matsuzawa
A 24 dB gain 51-68 GHz CMOS low noise amplifier using asymmetric-layout transistors. ESSCIRC (2010)
Yoichi Kawano, Toshihide Suzuki, Masaru Sato, Tatsuya Hirose, Kazukiyo Joshin
A 77GHz transceiver in 90nm CMOS. ISSCC (2009)
Masaru Sato, Tatsuya Hirose, Koji Mizuno
Advanced MMIC Receiver for 94-GHz Band Passive Millimeter-Wave Imager. IEICE Trans. Electron. (9) (2009)
Toshihide Suzuki, Yoichi Kawano, Masaru Sato, Tatsuya Hirose, Kazukiyo Joshin
60 and 77GHz Power Amplifiers in Standard 90nm CMOS. ISSCC (2008)
Toshihide Suzuki, Yoichi Kawano, Yasuhiro Nakasha, Shinji Yamaura, Tsuyoshi Takahashi, Kozo Makiyama, Tatsuya Hirose
A 50-Gbit/s 450-mW Full-Rate 4: 1 Multiplexer With Multiphase Clock Architecture in 0.13-µm InP HEMT Technology. IEEE J. Solid State Circuits 42 (3) (2007)
Yusuke Inoue, Masaru Sato, Toshihiro Ohki, Kozo Makiyama, Tsuyoshi Takahashi, Hisao Shigematsu, Tatsuya Hirose
A 90-GHz InP-HEMT lossy match amplifier with a 20-dB gain using a broadband matching technique. IEEE J. Solid State Circuits 40 (10) (2005)
Toshihide Suzuki, Tsuyoshi Takahashi, Tatsuya Hirose, Masahiko Takikawa
A 80-gbit/s D-type flip-flop circuit using InP HEMT technology. IEEE J. Solid State Circuits 39 (10) (2004)
Hisao Shigematsu, Masaru Sato, Tatsuya Hirose, Yuu Watanabe
modulator driver. IEEE J. Solid State Circuits 37 (9) (2002)
Yasuhiro Nakasha, Toshihide Suzuki, Hideki Kano, Kouji Tsukashima, Akio Ohya, Ken Sawada, Kozo Makiyama, Tsuyoshi Takahashi, Masahiro Nishi, Tatsuya Hirose, Masahiko Takikawa, Yuu Watanabe
A 43-Gb/s full-rate-clock 4: 1 multiplexer in InP-based HEMT technology. IEEE J. Solid State Circuits 37 (12) (2002)