A 24 dB gain 51-68 GHz CMOS low noise amplifier using asymmetric-layout transistors.
Ning LiKeigo BunsenNaoki TakayamaQinghong BuToshihide SuzukiMasaru SatoTatsuya HiroseKenichi OkadaAkira MatsuzawaPublished in: ESSCIRC (2010)
Keyphrases
- power consumption
- low power
- high speed
- high power
- circuit design
- high noise
- cmos technology
- high sensitivity
- power supply
- low signal to noise ratio
- wide dynamic range
- low cost
- noise level
- high density
- gaussian noise
- signal noise ratio
- noisy data
- neural network
- floating gate
- dynamic range
- focal plane
- metal oxide semiconductor
- database
- random noise
- image sensor
- integrated circuit
- signal to noise ratio
- missing data