Sudhakar Yalamanchili

Publication Activity (10 Years)

Years Active: 1982-2021
Publications (10 Years): 34

Top Venues

CoRR

MEMSYS

ISCA

GPGPU@ASPLOS

Publications

He Xiao, Monodeep Kar, Saibal Mukhopadhyay, Sudhakar Yalamanchili
VDPred: Predicting Voltage Droop for Power-Effient 3D Multi-core Processor Design. ICCAE (2021)
Bahar Asgari, Ramyad Hadidi, Tushar Krishna, Hyesoon Kim, Sudhakar Yalamanchili
Efficiently Solving Partial Differential Equations in a Partially Reconfigurable Specialized Hardware. IEEE Trans. Computers 70 (4) (2021)
Bahar Asgari, Saibal Mukhopadhyay, Sudhakar Yalamanchili
MAHASIM: Machine-Learning Hardware Acceleration Using a Software-Defined Intelligent Memory System. J. Signal Process. Syst. 93 (6) (2021)
Bahar Asgari, Ramyad Hadidi, Tushar Krishna, Hyesoon Kim, Sudhakar Yalamanchili
ALRESCHA: A Lightweight Reconfigurable Sparse-Computation Accelerator. HPCA (2020)
Blaise-Pascal Tine, Sudhakar Yalamanchili, Hyesoon Kim
Tango: An Optimizing Compiler for Just-In-Time RTL Simulation. DATE (2020)
Maciej Besta, Syed Minhaj Hassan, Sudhakar Yalamanchili, Rachata Ausavarungnirun, Onur Mutlu, Torsten Hoefler
Slim NoC: A Low-Diameter On-Chip Network Topology for High Energy Efficiency and Scalability. CoRR (2020)
Saibal Mukhopadhyay, Yun Long, Burhan Ahmad Mudassar, C. S. Nair, Bartlet H. DeProspo, Hakki Mert Torun, M. Kathaperumal, V. Smet, Duckhwan Kim, Sudhakar Yalamanchili, Madhavan Swaminathan
Heterogeneous integration for artificial intelligence: Challenges and opportunities. IBM J. Res. Dev. 63 (6) (2019)
Bahar Asgari, Ramyad Hadidi, Hyesoon Kim, Sudhakar Yalamanchili
ERIDANUS: Efficiently Running Inference of DNNs Using Systolic Arrays. IEEE Micro 39 (5) (2019)
Blaise-Pascal Tine, Sudhakar Yalamanchili, Hyesoon Kim, Jeffrey S. Vetter
POSTER: Tango: An Optimizing Compiler for Just-In-Time RTL Simulation. PACT (2019)
Bahar Asgari, Ramyad Hadidi, Hyesoon Kim, Sudhakar Yalamanchili
LODESTAR: Creating Locally-Dense CNNs for Efficient Inference on Systolic Arrays. DAC (2019)
Yun Long, Taesik Na, Prakshi Rastogi, Karthik Rao, Asif Islam Khan, Sudhakar Yalamanchili, Saibal Mukhopadhyay
A ferroelectric FET based power-efficient architecture for data-intensive computing. ICCAD (2018)
Maciej Besta, Syed Minhaj Hassan, Sudhakar Yalamanchili, Rachata Ausavarungnirun, Onur Mutlu, Torsten Hoefler
Slim NoC: A Low-Diameter On-Chip Network Topology for High Energy Efficiency and Scalability. ASPLOS (2018)
Karthik Rao, William J. Song, Yorai Wardi, Sudhakar Yalamanchili
TRINITY: Coordinated Performance, Energy and Temperature Management in 3D Processor-Memory Stacks. CoRR (2018)
Duckhwan Kim, Taesik Na, Sudhakar Yalamanchili, Saibal Mukhopadhyay
DeepTrain: A Programmable Embedded Platform for Training Deep Neural Networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37 (11) (2018)
Bahar Asgari, Saibal Mukhopadhyay, Sudhakar Yalamanchili
Memory Slices: A Modular Building Block for Scalable, Intelligent Memory Systems. CoRR (2018)
Xinwei Chen, Yorai Wardi, Sudhakar Yalamanchili
Instruction-throughput regulation in computer processors with data-center applications. Discret. Event Dyn. Syst. 28 (1) (2018)
Chad D. Kersey, Hyesoon Kim, Sudhakar Yalamanchili
Lightweight SIMT core designs for intelligent 3D stacked DRAM. MEMSYS (2017)
X. Chen, Yorai Wardi, Sudhakar Yalamanchili
Power Regulation in High Performance Multicore Processors. CoRR (2017)
Ramyad Hadidi, Bahar Asgari, Burhan Ahmad Mudassar, Saibal Mukhopadhyay, Sudhakar Yalamanchili, Hyesoon Kim
Demystifying the Characteristics of 3D-Stacked Memories: A Case Study for Hybrid Memory Cube. CoRR (2017)
Blaise-Pascal Tine, Sudhakar Yalamanchili
Pagevault: securing off-chip memory using page-based authentication. MEMSYS (2017)
Karthik Rao, Jun Wang, Sudhakar Yalamanchili, Yorai Wardi, Handong Ye
Application-Specific Performance-Aware Energy Optimization on Android Mobile Devices. HPCA (2017)
Xinwei Chen, Yorai Wardi, Sudhakar Yalamanchili
Power regulation in high performance multicore processors. CDC (2017)
Ramyad Hadidi, Bahar Asgari, Burhan Ahmad Mudassar, Saibal Mukhopadhyay, Sudhakar Yalamanchili, Hyesoon Kim
Demystifying the characteristics of 3D-stacked memories: A case study for Hybrid Memory Cube. IISWC (2017)
Duckhwan Kim, Taesik Na, Sudhakar Yalamanchili, Saibal Mukhopadhyay
NeuroTrainer: An Intelligent Memory Module for Deep Learning Training. CoRR (2017)
He Xiao, Wen Yueh, Saibal Mukhopadhyay, Sudhakar Yalamanchili
Thermally Adaptive Cache Access Mechanisms for 3D Many-Core Architectures. IEEE Comput. Archit. Lett. 15 (2) (2016)
Syed Minhaj Hassan, Sudhakar Yalamanchili
Understanding the Impact of Air and Microfluidics Cooling on Performance of 3D Stacked Memory Systems. MEMSYS (2016)
Eric Anger, Jeremiah J. Wilke, Sudhakar Yalamanchili
Power-Constrained Performance Scheduling of Data Parallel Tasks. E2SC@SC (2016)
William J. Song, Saibal Mukhopadhyay, Sudhakar Yalamanchili
Amdahl's law for lifetime reliability scaling in heterogeneous multicore processors. HPCA (2016)
Xinwei Chen, Yorai Wardi, Sudhakar Yalamanchili
IPA in the loop: Control design for throughput regulation in computer processors. WODES (2016)
Xinwei Chen, Yorai Wardi, Sudhakar Yalamanchili
IPA in the Loop: Control Design for Throughput Regulation in Computer Processors. CoRR (2016)
Jun Wang, Zhenjiang Dong, Sudhakar Yalamanchili, George F. Riley
FNM: An Enhanced Null-Message Algorithm for Parallel Simulation of Multicore Systems. ACM Trans. Model. Comput. Simul. 26 (2) (2016)
Duckhwan Kim, Jaeha Kung, Sek M. Chai, Sudhakar Yalamanchili, Saibal Mukhopadhyay
Neurocube: A Programmable Digital Neuromorphic Architecture with High-Density 3D Memory. ISCA (2016)
Jin Wang, Norm Rubin, Albert Sidelnik, Sudhakar Yalamanchili
LaPerm: Locality Aware Scheduler for Dynamic Parallelism on GPUs. ISCA (2016)
Daniel Zinn, Haicheng Wu, Jin Wang, Molham Aref, Sudhakar Yalamanchili
General-purpose join algorithms for large graph triangle listing on heterogeneous systems. GPGPU@PPoPP (2016)
Syed Minhaj Hassan, Sudhakar Yalamanchili, Saibal Mukhopadhyay
Near Data Processing: Impact and Optimization of 3D Memory System Architecture on the Uncore. MEMSYS (2015)
Hyojong Kim, Hyesoon Kim, Sudhakar Yalamanchili, Arun F. Rodrigues
Understanding Energy Aspects of Processing-near-Memory for HPC Workloads. MEMSYS (2015)
William J. Song, Saibal Mukhopadhyay, Sudhakar Yalamanchili
Architectural Reliability: Lifetime Reliability Characterization and Management ofMany-Core Processors. IEEE Comput. Archit. Lett. 14 (2) (2015)
William J. Song, Saibal Mukhopadhyay, Sudhakar Yalamanchili
Managing performance-reliability tradeoffs in multicore processors. IRPS (2015)
Eric Anger, Damian Dechev, Gilbert Hendry, Jeremiah J. Wilke, Sudhakar Yalamanchili
Application Modeling for Scalable Simulation of Massively Parallel Systems. HPCC/CSS/ICESS (2015)
Indrani Paul, Wei Huang, Manish Arora, Sudhakar Yalamanchili
Harmonia: balancing compute and memory power in high-performance GPUs. ISCA (2015)
X. Chen, H. Xiao, Yorai Wardi, Sudhakar Yalamanchili
Throughput Regulation in Shared Memory Multicore Processors. HiPC (2015)
Chad D. Kersey, Sudhakar Yalamanchili, Hyesoon Kim
SIMT-based Logic Layers for Stacked DRAM Architectures: A Prototype. MEMSYS (2015)
Karthik Rao, William J. Song, Sudhakar Yalamanchili, Yorai Wardi
Temperature regulation in multicore processors using adjustable-gain integral controllers. CCA (2015)
Jin Wang, Norm Rubin, Albert Sidelnik, Sudhakar Yalamanchili
Dynamic thread block launch: a lightweight execution mechanism to support irregular applications on GPUs. ISCA (2015)
Eric Anger, Sudhakar Yalamanchili, Scott Pakin, Patrick S. McCormick
Architecture-independent modeling of intra-node data movement. LLVM@SC (2014)
Chad D. Kersey, Sudhakar Yalamanchili, Hyojong Kim, Nimit Nigania, Hyesoon Kim
Harmonica: An FPGA-Based Data Parallel Soft Core. FCCM (2014)
Indrani Paul, Vignesh T. Ravi, Srilatha Manne, Manish Arora, Sudhakar Yalamanchili
Coordinated energy management in heterogeneous processors. Sci. Program. 22 (2) (2014)
Haicheng Wu, Gregory F. Diamos, Tim Sheard, Molham Aref, Sean Baxter, Michael Garland, Sudhakar Yalamanchili
Red Fox: An Execution Environment for Relational Query Processing on GPUs. CGO (2014)
Syed Minhaj Hassan, Sudhakar Yalamanchili
Bubble sharing: Area and energy efficient adaptive routers using centralized buffers. NOCS (2014)
Jieun Lim, Nagesh B. Lakshminarayana, Hyesoon Kim, William J. Song, Sudhakar Yalamanchili, Wonyong Sung
Power Modeling for GPU Architectures Using McPAT. ACM Trans. Design Autom. Electr. Syst. 19 (3) (2014)
Zhimin Wan, He Xiao, Yogendra Joshi, Sudhakar Yalamanchili
Co-design of multicore architectures and microfluidic cooling for 3D stacked ICs. Microelectron. J. 45 (12) (2014)
Haicheng Wu, Daniel Zinn, Molham Aref, Sudhakar Yalamanchili
Multipredicate Join Algorithms for Accelerating Relational Graph Processing on GPUs. ADMS@VLDB (2014)
Jin Wang, Sudhakar Yalamanchili
Characterization and analysis of dynamic parallelism in unstructured GPU applications. IISWC (2014)
Naila Farooqui, Karsten Schwan, Sudhakar Yalamanchili
Efficient Instrumentation of GPGPU Applications Using Information Flow Analysis and Symbolic Execution. GPGPU@ASPLOS (2014)
Zhenjiang Dong, Jun Wang, George F. Riley, Sudhakar Yalamanchili
An efficient front-end for timing-directed parallel simulation of multi-core system. SimuTools (2014)
Jin Wang, Norman Rubin, Sudhakar Yalamanchili
ParallelJS: An Execution Framework for JavaScript on Heterogeneous Systems. GPGPU@ASPLOS (2014)
William J. Song, Saibal Mukhopadhyay, Sudhakar Yalamanchili
Energy Introspector: A parallel, composable framework for integrated power-reliability-thermal modeling for multicore architectures. ISPASS (2014)
Borislav Alexandrov, Owen Sullivan, William J. Song, Sudhakar Yalamanchili, Satish Kumar, Saibal Mukhopadhyay
Control Principles and On-Chip Circuits for Active Cooling Using Integrated Superlattice-Based Thin-Film Thermoelectric Devices. IEEE Trans. Very Large Scale Integr. Syst. 22 (9) (2014)
Jun Wang, Jesse G. Beu, Rishiraj A. Bheda, Tom Conte, Zhenjiang Dong, Chad D. Kersey, Mitchelle Rasquinha, George F. Riley, William J. Song, He Xiao, Peng Xu, Sudhakar Yalamanchili
Manifold: A parallel simulation framework for multicore systems. ISPASS (2014)
Indrani Paul, Srilatha Manne, Manish Arora, William Lloyd Bircher, Sudhakar Yalamanchili
Cooperative boosting: needy versus greedy power management. ISCA (2013)
Zhenjiang Dong, Jun Wang, George F. Riley, Sudhakar Yalamanchili
A Study of the Effect of Partitioning on Parallel Simulation of Multicore Systems. MASCOTS (2013)
Jaekyu Lee, Si Li, Hyesoon Kim, Sudhakar Yalamanchili
Design space exploration of on-chip ring interconnection for a CPU-GPU heterogeneous architecture. J. Parallel Distributed Comput. 73 (12) (2013)
Jun Wang, Zhenjiang Dong, Sudhakar Yalamanchili, George F. Riley
Optimizing parallel simulation of multicore systems using domain-specific knowledge. SIGSIM-PADS (2013)
Syed Minhaj Hassan, Sudhakar Yalamanchili
Centralized buffer router: A low latency, low power router for high radix NOCs. NOCS (2013)
Indrani Paul, Vignesh T. Ravi, Srilatha Manne, Manish Arora, Sudhakar Yalamanchili
Coordinated energy management in heterogeneous processors. SC (2013)
Gregory Frederick Diamos, Haicheng Wu, Jin Wang, Ashwin Lele, Sudhakar Yalamanchili
Relational algorithms for multi-bulk-synchronous processors. PPOPP (2013)
Jaekyu Lee, Si Li, Hyesoon Kim, Sudhakar Yalamanchili
Adaptive virtual channel partitioning for network-on-chip in heterogeneous architectures. ACM Trans. Design Autom. Electr. Syst. 18 (4) (2013)
Jin Wang, Norman Rubin, Haicheng Wu, Sudhakar Yalamanchili
Accelerating simulation of agent-based models on heterogeneous architectures. GPGPU@ASPLOS (2013)
Jeffrey S. Young, Se Hoon Shon, Sudhakar Yalamanchili, Alex Merritt, Karsten Schwan, Holger Fröning
Oncilla: A GAS runtime for efficient resource allocation and data movement in accelerated clusters. CLUSTER (2013)
Andrew Kerr, Eric Anger, Gilbert Hendry, Sudhakar Yalamanchili
Eiger: A framework for the automated synthesis of statistical performance models. HiPC (2012)
Jeffrey S. Young, Haicheng Wu, Sudhakar Yalamanchili
Satisfying Data-Intensive Queries Using GPU Clusters. SC Companion (2012)
Haicheng Wu, Gregory F. Diamos, Jin Wang, Si Li, Sudhakar Yalamanchili
Characterization and transformation of unstructured control flow in bulk synchronous GPU applications. Int. J. High Perform. Comput. Appl. 26 (2) (2012)
Chad D. Kersey, Arun Rodrigues, Sudhakar Yalamanchili
A universal parallel front-end for execution driven microarchitecture simulation. RAPIDO (2012)
Jun Wang, Jesse G. Beu, Sudhakar Yalamanchili, Tom Conte
Designing Configurable, Modifiable and Reusable Components for Simulation of Multicore Systems. SC Companion (2012)
Nawaf I. Almoosa, William J. Song, Sudhakar Yalamanchili, Yorai Wardi
Throughput regulation in multicore processors via IPA. CDC (2012)
William J. Song, Sudhakar Yalamanchili, Arun F. Rodrigues, Saibal Mukhopadhyay
Instruction-based energy estimation methodology for asymmetric manycore processor simulations. SimuTools (2012)
Haicheng Wu, Gregory Frederick Diamos, Srihari Cadambi, Sudhakar Yalamanchili
Kernel Weaver: Automatically Fusing Database Primitives for Efficient GPU Computation. MICRO (2012)
Indrani Paul, Sudhakar Yalamanchili, Lizy K. John
Performance impact of virtual machine placement in a datacenter. IPCCC (2012)
Haicheng Wu, Gregory F. Diamos, Jin Wang, Srihari Cadambi, Sudhakar Yalamanchili, Srimat T. Chakradhar
Optimizing Data Warehousing Applications for GPUs Using Kernel Fusion/Fission. IPDPS Workshops (2012)
Naila Farooqui, Andrew Kerr, Greg Eisenhauer, Karsten Schwan, Sudhakar Yalamanchili
Lynx: A dynamic instrumentation system for data-parallel applications on GPGPU architectures. ISPASS (2012)
Andrew Kerr, Gregory Frederick Diamos, Sudhakar Yalamanchili
Dynamic compilation of data-parallel kernels for vector processors. CGO (2012)
Nawaf I. Almoosa, William J. Song, Yorai Wardi, Sudhakar Yalamanchili
A power capping controller for multicore processors. ACC (2012)
Jeffrey S. Young, Sudhakar Yalamanchili
Commodity Converged Fabrics for Global Address Spaces in Accelerator Clouds. HPCC-ICESS (2012)
Subho Chatterjee, Mitchelle Rasquinha, Sudhakar Yalamanchili, Saibal Mukhopadhyay
A Scalable Design Methodology for Energy Minimization of STTRAM: A Circuit and Architecture Perspective. IEEE Trans. Very Large Scale Integr. Syst. 19 (5) (2011)
Syed Minhaj Hassan, Dhruv Choudhary, Mitchelle Rasquinha, Sudhakar Yalamanchili
Regulating Locality vs. Parallelism Tradeoffs in Multiple Memory Controller Environments. PACT (2011)
Gregory Frederick Diamos, Benjamin Ashbaugh, Subramaniam Maiyuran, Andrew Kerr, Haicheng Wu, Sudhakar Yalamanchili
SIMD re-convergence at thread frontiers. MICRO (2011)
Jeffrey S. Vetter, Richard Glassbrook, Jack J. Dongarra, Karsten Schwan, Bruce Loftis, Stephen McNally, Jeremy S. Meredith, James H. Rogers, Philip C. Roth, Kyle Spafford, Sudhakar Yalamanchili
Keeneland: Bringing Heterogeneous GPU Computing to the Computational Science Community. Comput. Sci. Eng. 13 (5) (2011)
Naila Farooqui, Andrew Kerr, Gregory Frederick Diamos, Sudhakar Yalamanchili, Karsten Schwan
A framework for dynamically instrumenting GPU compute applications within GPU Ocelot. GPGPU (2011)
Andrew Kerr, Gregory F. Diamos, Sudhakar Yalamanchili
Modeling GPU-CPU workloads and systems. GPGPU (2010)
Gregory Frederick Diamos, Andrew Kerr, Sudhakar Yalamanchili, Nathan Clark
Ocelot: a dynamic optimization framework for bulk-synchronous applications in heterogeneous systems. PACT (2010)
Gregory F. Diamos, Sudhakar Yalamanchili
Speculative execution on multi-GPU systems. IPDPS (2010)
Nawaf I. Almoosa, Yorai Wardi, Sudhakar Yalamanchili
Controller design for tracking induced miss-rates in cache memories. ICCA (2010)
Jeffrey S. Young, Sudhakar Yalamanchili
Dynamic Partitioned Global Address Spaces for power efficient DRAM virtualization. Green Computing Conference (2010)
Mitchelle Rasquinha, Dhruv Choudhary, Subho Chatterjee, Saibal Mukhopadhyay, Sudhakar Yalamanchili
An energy efficient cache design using spin torque transfer (STT) RAM. ISLPED (2010)
Karsten Schwan, Ada Gavrilovska, Sudhakar Yalamanchili
HyVM - Hybrid Virtual Machines - Efficient Use of Future Heterogeneous Chip Multiprocessors. ARCS (2010)
Dean L. Lewis, Sudhakar Yalamanchili, Hsien-Hsin S. Lee
High Performance Non-blocking Switch Design in 3D Die-Stacking Technology. ISVLSI (2009)
Andrew Kerr, Gregory F. Diamos, Sudhakar Yalamanchili
A characterization and analysis of PTX kernels. IISWC (2009)
Subho Chatterjee, Mitchelle Rasquinha, Sudhakar Yalamanchili, Saibal Mukhopadhyay
A methodology for robust, energy efficient design of Spin-Torque-Transfer RAM arrays at scaled technologies. ICCAD (2009)
Kangtao Kendall Chuang, Sudhakar Yalamanchili, Ada Gavrilovska, Karsten Schwan
ShareStreams-V: A Virtualized QoS Packet Scheduling Accelerator. FCCM (2008)
Gregory F. Diamos, Sudhakar Yalamanchili
Harmony: an execution model and runtime for heterogeneous many core systems. HPDC (2008)

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Publication Activity (10 Years)

Top Topics

Top Venues

Sudhakar Yalamanchili