Mark D. Aagaard

Publication Activity (10 Years)

Years Active: 1991-2024
Publications (10 Years): 15

Top Topics

Adaptive Window

Hardware Design

Top Venues

IACR Cryptol. ePrint Arch.

Cryptogr. Commun.

IEEE Trans. Computers

Publications

Nusa Zidaric, Kalikinkar Mandal, Guang Gong, Mark D. Aagaard
The welch-gong stream cipher - evolutionary path. Cryptogr. Commun. 16 (1) (2024)
Nusa Zidaric, Mark D. Aagaard
Tower field support for synthesis of datapaths. CF (2023)
Nusa Zidaric, Guang Gong, Mark D. Aagaard, Aleksandar Jurisic, Olexandr Konovalov
FFCSA - Finite Field Constructions, Search, and Algorithms. ACM Commun. Comput. Algebra 57 (2) (2023)
Mark D. Aagaard, Nusa Zidaric
ASIC Benchmarking of Round 2 Candidates in the NIST Lightweight Cryptography Standardization Process: (Preliminary Results). IACR Cryptol. ePrint Arch. 2021 (2021)
Ahmed A. Ayoub, Mark D. Aagaard
Application-Specific Instruction Set Architecture for an Ultralight Hardware Security Module. HOST (2020)
Kalikinkar Mandal, Bo Yang, Guang Gong, Mark D. Aagaard
Analysis and Efficient Implementations of a Class of Composited de Bruijn Sequences. IEEE Trans. Computers 69 (12) (2020)
Mark D. Aagaard, Marat Sattarov, Nusa Zidaric
Hardware Design and Analysis of the ACE and WAGE Ciphers. CoRR (2019)
Nusa Zidaric, Mark D. Aagaard, Guang Gong
Hardware Optimizations and Analysis for the WG-16 Cipher with Tower Field Arithmetic. IEEE Trans. Computers 68 (1) (2019)
Kalikinkar Mandal, Bo Yang, Guang Gong, Mark D. Aagaard
On ideal t-tuple distribution of filtering de Bruijn sequence generators. Cryptogr. Commun. 10 (4) (2018)
Nusa Zidaric, Mark D. Aagaard, Guang Gong
Rapid Hardware Design for Cryptographic Modules with Filtering Structures over Small Finite Fields. WAIFI (2018)
Bo Yang, Kalikinkar Mandal, Mark D. Aagaard, Guang Gong
Efficient Composited de Bruijn Sequence Generators. IEEE Trans. Computers 66 (8) (2017)
Gangqiang Yang, Mark D. Aagaard, Guang Gong
Efficient Hardware Implementations of the Warbler Pseudorandom Number Generator. IACR Cryptol. ePrint Arch. 2015 (2015)
Gangqiang Yang, Bo Zhu, Valentin Suder, Mark D. Aagaard, Guang Gong
The Simeck Family of Lightweight Block Ciphers. IACR Cryptol. ePrint Arch. 2015 (2015)
Gangqiang Yang, Bo Zhu, Valentin Suder, Mark D. Aagaard, Guang Gong
The Simeck Family of Lightweight Block Ciphers. CHES (2015)
Farzad Khalvati, Mark D. Aagaard, Hamid R. Tizhoosh
Window memoization: toward high-performance image processing software. J. Real Time Image Process. 10 (1) (2015)
Kalikinkar Mandal, Guang Gong, Xinxin Fan, Mark D. Aagaard
Optimal parameters for the WG stream cipher family. Cryptogr. Commun. 6 (2) (2014)
Mark D. Aagaard, Guang Gong, Rajesh K. Mota
Hardware implementations of the WG-5 cipher for passive RFID tags. HOST (2013)
Guang Gong, Mark D. Aagaard, Xinxin Fan
Resilience to distinguishing attacks on WG-7 cipher and their generalizations. Cryptogr. Commun. 5 (4) (2013)
Gangqiang Yang, Xinxin Fan, Mark D. Aagaard, Guang Gong
Design space exploration of the lightweight stream cipher WG-8 for FPGAs and ASICs. WESS (2013)
Xinxin Fan, Nusa Zidaric, Mark D. Aagaard, Guang Gong
Efficient hardware implementation of the stream cipher WG-16 with composite field arithmetic. TrustED@CCS (2013)
Kalikinkar Mandal, Guang Gong, Xinxin Fan, Mark D. Aagaard
On selection of optimal parameters for the WG stream cipher family. CWIT (2013)
Guang Gong, Mark D. Aagaard, Xinxin Fan
Resilience to Distinguishing Attacks on WG-7 Cipher and Their Generalizations. IACR Cryptol. ePrint Arch. 2012 (2012)
Farzad Khalvati, Mark D. Aagaard
Window memoization: an efficient hardware architecture for high-performance image processing. J. Real Time Image Process. 5 (3) (2010)
Eunsuk Kang, Mark D. Aagaard
Improving the Usability of HOL Through Controlled Automation Tactics. TPHOLs (2007)
Carl-Johan H. Seger, Robert B. Jones, John W. O'Leary, Thomas F. Melham, Mark D. Aagaard, Clark W. Barrett, Don Syme
An industrially effective environment for formal hardware verification. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24 (9) (2005)
Jason T. Higgins, Mark D. Aagaard
Simplifying the design and automating the verification of pipelines with structural hazards. ACM Trans. Design Autom. Electr. Syst. 10 (4) (2005)
Jason T. Higgins, Mark D. Aagaard
Simplifying design and verification for structural hazards and datapaths in pipelined circuits. HLDVT (2004)
Mark D. Aagaard, Vlad C. Ciubotariu, Jason T. Higgins, Farzad Khalvati
Combining Equivalence Verification and Completion Functions. FMCAD (2004)
Hazem I. Shehata, Mark D. Aagaard
A general decomposition strategy for verifying register renaming. DAC (2004)
Mark D. Aagaard, Nancy A. Day, Robert B. Jones
Synchronization-at-Retirement for Pipeline Verification. FMCAD (2004)
Mark D. Aagaard, Byron Cook, Nancy A. Day, Robert B. Jones
A framework for superscalar microprocessor correctness statements. Int. J. Softw. Tools Technol. Transf. 4 (3) (2003)
Mark D. Aagaard
A Hazards-Based Correctness Statement for Pipelined Circuits. CHARME (2003)
Mark D. Aagaard, Nancy A. Day, Meng Lou
Relating Multi-step and Single-Step Microprocessor Correctness Statements. FMCAD (2002)
Robert Beers, Rajnish Ghughal, Mark D. Aagaard
Applications of Hierarchical Verification in Model Checking. CHARME (2001)
Robert B. Jones, John W. O'Leary, Carl-Johan H. Seger, Mark D. Aagaard, Thomas F. Melham
Practical Formal Verification in Microprocessor Design. IEEE Des. Test Comput. 18 (4) (2001)
Mark D. Aagaard, Byron Cook, Nancy A. Day, Robert B. Jones
A Framework for Microprocessor Correctness Statements. CHARME (2001)
Mark D. Aagaard, Robert B. Jones, Thomas F. Melham, John W. O'Leary, Carl-Johan H. Seger
A Methodology for Large-Scale Hardware Verification. FMCAD (2000)
Mark D. Aagaard, Robert B. Jones, Roope Kaivola, Katherine R. Kohatsu, Carl-Johan H. Seger
Formal verification of iterative algorithms in microprocessors. DAC (2000)
Robert Beers, Rajnish Ghughal, Mark D. Aagaard
Applications of Hierarchical Verification in Model Checking. FMCAD (2000)
Roope Kaivola, Mark D. Aagaard
Divider Circuit Verification with Model Checking and Theorem Proving. TPHOLs (2000)
Nancy A. Day, Mark D. Aagaard, Byron Cook
Combining Stream-Based and State-Based Verification Techniques. FMCAD (2000)
Mark D. Aagaard, Robert B. Jones, Carl-Johan H. Seger
Lifted-FL: A Pragmatic Implementation of Combined Model Checking and Theorem Proving. TPHOLs (1999)
Mark D. Aagaard, Thomas F. Melham, John W. O'Leary
Xs are for Trajectory Evaluation, Booleans are for Theorem Proving. CHARME (1999)
Mark D. Aagaard, Robert B. Jones, Carl-Johan H. Seger
Parametric Representations of Boolean Constraints. DAC (1999)
Mark D. Aagaard, Robert B. Jones, Carl-Johan H. Seger
Combining Theorem Proving and Trajectory Evaluation in an Industrial Environment. DAC (1998)
Mark D. Aagaard, Miriam Leeser
Verifying a Logic-Synthesis Algorithm and Implementation: A Case Study in Software Verification. IEEE Trans. Software Eng. 21 (10) (1995)
Mark D. Aagaard, Carl-Johan H. Seger
The formal verification of a pipelined double-precision IEEE floating-point multiplier. ICCAD (1995)
John W. O'Leary, Miriam Leeser, Jason Hickey, Mark D. Aagaard
Non-Restoring Integer Square Root: A Case Study in Design by Principled Optimization. TPCD (1994)
Mark D. Aagaard, Miriam Leeser
Reasoning About Pipelines with Structural Hazards. TPCD (1994)
Mark D. Aagaard, Miriam Leeser
A Methodology for Efficient Hardware Verification. Formal Methods Syst. Des. 5 (1/2) (1994)
Mark D. Aagaard, Miriam Leeser
PBS: proven Boolean simplification. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13 (4) (1994)
John W. O'Leary, Mark H. Linderman, Miriam Leeser, Mark D. Aagaard
HML: A Hardware Description Language Based on Standard ML. CHDL (1993)
Miriam Leeser, Richard Chapman, Mark D. Aagaard, Mark H. Linderman, Stephan Meier
High level synthesis and generating FPGAs with the BEDROC system. J. VLSI Signal Process. 6 (2) (1993)
Mark D. Aagaard, Miriam Leeser
A Framework for Specifying and Designing Pipelines. ICCD (1993)
Mark D. Aagaard, Miriam Leeser, Phillip J. Windley
Toward a Super Duper Hardware Tactic. HUG (1993)
Mark D. Aagaard, Miriam Leeser
Verifying a Logic Synthesis Tool in Nuprl: A Case Study in Software Verification. CAV (1992)
Mark D. Aagaard, Miriam Leeser
A Methodology for Reusable Hardware Proofs. TPHOLs (1992)
Mark D. Aagaard, Miriam Leeser
A Formally Verified System for Logic Synthesis. ICCD (1991)