Hubert Kaeslin

Publication Activity (10 Years)

Years Active: 1986-2018
Publications (10 Years): 2

Top Topics

Tightly Coupled

Video Processing

Top Venues

IEEE Trans. Circuits Syst. Video Technol.

Publications

Michael Schaffner, Florian Scheidegger, Lukas Cavigelli, Hubert Kaeslin, Luca Benini, Aljosa Smolic
Towards Edge-Aware Spatio-Temporal Filtering in Real-Time. IEEE Trans. Image Process. 27 (1) (2018)
Michael Schaffner, Frank K. Gürkaynak, Pierre Greisen, Hubert Kaeslin, Luca Benini, Aljosa Smolic
Hybrid ASIC/FPGA System for Fully Automatic Stereo-to-Multiview Conversion Using IDW. IEEE Trans. Circuits Syst. Video Technol. 26 (11) (2016)
Michael Schaffner, Frank K. Gürkaynak, Hubert Kaeslin, Luca Benini, Aljosa Smolic
Automatic multiview synthesis - Prototype demo. VCIP (2015)
Michael Schaffner, Frank K. Gürkaynak, Hubert Kaeslin, Luca Benini, Aljosa Smolic
Automatic multiview synthesis - Towards a mobile system on a chip. VCIP (2015)
Christoph Keller, Frank K. Gürkaynak, Hubert Kaeslin, Norbert Felber
Dynamic memory-based physically unclonable function for the generation of unique identifiers and true random numbers. ISCAS (2014)
Michael Gautschi, Michael Muehlberghuber, Andreas Traber, Sven Stucki, Matthias Baer, Renzo Andri, Luca Benini, Beat Muheim, Hubert Kaeslin
SIR10US: A tightly coupled elliptic-curve cryptography co-processor for the OpenRISC. ASAP (2014)
Michael Schaffner, Frank K. Gürkaynak, Aljoscha Smolic, Hubert Kaeslin, Luca Benini
An Approximate Computing Technique for Reducing the Complexity of a Direct-Solver for Sparse Linear Systems in Real-Time Video Processing. DAC (2014)
Michael Schaffner, Pascal Hager, Lukas Cavigelli, Pierre Greisen, Frank K. Gürkaynak, Hubert Kaeslin
A real-time 720p feature extraction core based on Semantic Kernels Binarized. VLSI-SoC (2013)
Pierre Greisen, Marian Runo, Patrice Guillet, Simon Heinzle, Aljoscha Smolic, Hubert Kaeslin, Markus H. Gross
Evaluation and FPGA Implementation of Sparse Linear Solvers for Video Processing Applications. IEEE Trans. Circuits Syst. Video Technol. 23 (8) (2013)
David E. Bellasi, Patrick Maechler, Andreas Burg, Norbert Felber, Hubert Kaeslin, Christoph Studer
Live demonstration: Real-time audio restoration using sparse signal recovery. ISCAS (2013)
Michael Schaffner, Pierre Greisen, Simon Heinzle, Frank K. Gürkaynak, Hubert Kaeslin, Aljoscha Smolic
MADmax: A 1080p stereo-to-multiview rendering ASIC in 65 nm CMOS based on image domain warping. ESSCIRC (2013)
Michael Schaffner, Pascal A. Hager, Lukas Cavigelli, Z. Fang, Pierre Greisen, Frank K. Gürkaynak, Aljoscha Smolic, Hubert Kaeslin, Luca Benini
A Complete Real-Time Feature Extraction and Matching System Based on Semantic Kernels Binarized. VLSI-SoC (Selected Papers) (2013)
Patrick Maechler, Norbert Felber, Hubert Kaeslin, Andreas Burg
Hardware-efficient random sampling of fourier-sparse signals. ISCAS (2012)
Patrick Maechler, Christoph Studer, David E. Bellasi, Arian Maleki, Andreas Burg, Norbert Felber, Hubert Kaeslin, Richard G. Baraniuk
VLSI Design of Approximate Message Passing for Signal Restoration and Compressive Sensing. IEEE J. Emerg. Sel. Topics Circuits Syst. 2 (3) (2012)
Lin Bai, Patrick Maechler, Michael Muehlberghuber, Hubert Kaeslin
High-speed compressed sensing reconstruction on FPGA using OMP and AMP. ICECS (2012)
Pierre Greisen, Michael Schaffner, Simon Heinzle, Marian Runo, Aljoscha Smolic, Andreas Burg, Hubert Kaeslin, Markus H. Gross
Analysis and VLSI Implementation of EWA Rendering for Real-Time HD Video Applications. IEEE Trans. Circuits Syst. Video Technol. 22 (11) (2012)
Patrick Maechler, David E. Bellasi, Andreas Burg, Norbert Felber, Hubert Kaeslin, Christoph Studer
Sparsity-based real-time audio restoration. DASIP (2012)
Patrick Maechler, Norbert Felber, Hubert Kaeslin
Compressive sensing for WiFi-based passive bistatic radar. EUSIPCO (2012)
Flavio Carbognani, Felix Bürgin, Norbert Felber, Hubert Kaeslin, Wolfgang Fichtner
Transmission Gates Combined With Level-Restoring CMOS Gates Reduce Glitches in Low-Power Low-Frequency Multipliers. IEEE Trans. Very Large Scale Integr. Syst. 16 (7) (2008)
Peter Luethi, Christoph Studer, Sebastian Duetsch, Eugen Zgraggen, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner
Gram-Schmidt-based QR decomposition for MIMO detection: VLSI implementation and comparison. APCCAS (2008)
Tim Weyrich, Simon Heinzle, Timo Aila, Daniel Bernhard Fasnacht, Stephan Oetiker, Mario Botsch, Cyril Flaig, Simon Mall, Kaspar Rohrer, Norbert Felber, Hubert Kaeslin, Markus H. Gross
A hardware architecture for surface splatting. ACM Trans. Graph. 26 (3) (2007)
Flavio Carbognani, Simon Haene, Manuel Arrigo, Claudio Pagnamenta, Felix Bürgin, Norbert Felber, Hubert Kaeslin, Wolfgang Fichtner
A 0.25 μm 0.92 mW per Mb/s Viterbi decoder featuring resonant clocking for ultra-low-power 54 Mb/s WLAN communication. CICC (2007)
Flavio Carbognani, Felix Bürgin, Norbert Felber, Hubert Kaeslin, Wolfgang Fichtner
42% power savings through glitch-reducing clocking strategy in a hearing aid application. ISCAS (2006)
Felix Bürgin, Flavio Carbognani, Martin Hediger, Hektor Meier, Robert Meyer-Piening, Rafael Santschi, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner
Low-power architectural trade-offs in a VLSI implementation of an adaptive hearing aid algorithm. DAC (2006)
Flavio Carbognani, Felix Bürgin, Norbert Felber, Hubert Kaeslin, Wolfgang Fichtner
Two-phase resonant clocking for ultra-low-power hearing aid applications. DATE (2006)
Frank K. Gürkaynak, Stephan Oetiker, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner
Design Challenges for a Differential-Power-Analysis Aware GALS-based AES Crypto ASIC. Electron. Notes Theor. Comput. Sci. 146 (2) (2006)
Frank K. Gürkaynak, Stephan Oetiker, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner
GALS at ETH Zurich: Success or Failure. ASYNC (2006)
Flavio Carbognani, Felix Bürgin, Luca Henzen, Herbert Koch, Hovig Magdassian, Christoph Pedretti, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner
45-μW DSP VLSI implementation of an adaptive directional microphone for hearing aids. ECCTD (2005)
Frank K. Gürkaynak, Stephan Oetiker, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner
Improving DPA security by using globally-asynchronous locally-synchronous systems. ESSCIRC (2005)
Flavio Carbognani, Felix Bürgin, Norbert Felber, Hubert Kaeslin, Wolfgang Fichtner
Two-Phase Clocking and a New Latch Design for Low-Power Portable Applications. PATMOS (2005)
Norbert Pramstaller, Frank K. Gürkaynak, Simon Haene, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner
Towards an AES crypto-chip resistant to differential power analysis. ESSCIRC (2004)
Frank K. Gürkaynak, Andreas Burg, Norbert Felber, Wolfgang Fichtner, D. Gasser, Franco Hug, Hubert Kaeslin
A 2 Gb/s balanced AES crypto-chip implementation. ACM Great Lakes Symposium on VLSI (2004)
Thomas Villiger, Hubert Kaeslin, Frank K. Gürkaynak, Stephan Oetiker, Wolfgang Fichtner
Self-Timed Ring for Globally-Asynchronous Locally-Synchronous Systems. ASYNC (2003)
Jürgen Wassner, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner
Waveform coding for low-power digital filtering of speech data. IEEE Trans. Signal Process. 51 (6) (2003)
Andreas Burg, Frank K. Gürkaynak, Hubert Kaeslin, Wolfgang Fichtner
Variable delay ripple carry adder with carry chain interrupt detection. ISCAS (5) (2003)
Adrian K. Lutz, Jürg Treichler, Frank K. Gürkaynak, Hubert Kaeslin, Gerard Basler, Antonia Erni, Stephan Reichmuth, Pieter Rommens, Stephan Oetiker, Wolfgang Fichtner
2Gbit/s Hardware Realizations of RIJNDAEL and SERPENT: A Comparative Analysis. CHES (2002)
Thomas Villiger, Stephan Oetiker, Frank K. Gürkaynak, Norbert Felber, Hubert Kaeslin, Wolfgang Fichtner
A Functional Test Methodology for Globally-Asynchronous Locally-Synchronous Systems. ASYNC (2002)
Manfred Stadler, Markus Thalmann, Thomas Röwer, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner
Design and Verification of a Stack Processor Virtual Component. IEEE Micro 21 (2) (2001)
Thomas Roewer, Manfred Stadler, Markus Thalmann, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner
A new paradigm for very flexible SONET/SDH IP-modules. CICC (2000)
Manfred Stadler, Thomas Röwer, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner, Markus Thalmann
Functional verification of intellectual properties (IP): a simulation-based solution for an application-specific instruction-set processor. ITC (1999)
Robert Rogenmoser, Hubert Kaeslin
The impact of transistor sizing on power efficiency in submicron CMOS circuits. IEEE J. Solid State Circuits 32 (7) (1997)
Robert Rogenmoser, Hubert Kaeslin, Tobias Blickle
Stochastic Methods for Transistor Size Optimization of CMOS VLSI Circuits. PPSN (1996)
Reto Zimmermann, Andreas Curiger, Heinz Bonnenberg, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner
A 177 Mb/s VLSI implementation of the International Data Encryption Algorithm. IEEE J. Solid State Circuits 29 (3) (1994)
H. Bonnenberg, Andreas Curiger, Norbert Felber, Hubert Kaeslin, R. Zimmermann, Wolfgang Fichtner
VINCI: Secure Test of a VLSI High-Speed Encryption System. ITC (1993)
H. Bonnenberg, Andreas Curiger, Norbert Felber, Hubert Kaeslin, Xuejia Lai
VLSI Implementation of a New Block Cipher. ICCD (1991)
Marc Biver, Hubert Kaeslin, Carlo Tommasini
Architectural design and realization of a single-chip Viterbi decoder. Integr. 8 (1) (1989)
Hubert Kaeslin
Behandlung der Umlaute bei der Verarbeitung deutscher Texte unter UNIX / How to Handle German Umlauts when Processing Documents under UNIX. it Inf. Technol. 30 (1) (1988)
Hubert Kaeslin
Application of Graph Theory to Topology Generation for Logic Gates. WG (1988)
Hubert Kaeslin
A systematic approach to the extraction of diphone elements from natural speech. IEEE Trans. Acoust. Speech Signal Process. 34 (2) (1986)
Hubert Kaeslin
A comparative study of the steady-state zones of German phones using centroids in the LPC parameter space. Speech Commun. 5 (1) (1986)