Login / Signup

A 2 Gb/s balanced AES crypto-chip implementation.

Frank K. GürkaynakAndreas BurgNorbert FelberWolfgang FichtnerD. GasserFranco HugHubert Kaeslin
Published in: ACM Great Lakes Symposium on VLSI (2004)
Keyphrases
  • advanced encryption standard
  • high speed
  • circuit design
  • low cost
  • data sets
  • physical design