Norbert Felber

Publication Activity (10 Years)

Years Active: 1991-2016
Publications (10 Years): 1

Top Topics

Signal Recovery

Radio Frequency Identification

Mutual Authentication

Top Venues

Publications

Dinko Oletic, Vedran Bilas, Michele Magno, Norbert Felber, Luca Benini
Low-power multichannel spectro-temporal feature extraction circuit for audio pattern wake-up. DATE (2016)
Christoph Keller, Frank K. Gürkaynak, Hubert Kaeslin, Norbert Felber
Dynamic memory-based physically unclonable function for the generation of unique identifiers and true random numbers. ISCAS (2014)
Johann Ertl, Thomas Plos, Martin Feldhofer, Norbert Felber, Luca Henzen
A Security-Enhanced UHF RFID Tag Chip. DSD (2013)
David E. Bellasi, Patrick Maechler, Andreas Burg, Norbert Felber, Hubert Kaeslin, Christoph Studer
Live demonstration: Real-time audio restoration using sparse signal recovery. ISCAS (2013)
Patrick Maechler, Norbert Felber, Hubert Kaeslin, Andreas Burg
Hardware-efficient random sampling of fourier-sparse signals. ISCAS (2012)
Michael Muehlberghuber, Christoph Keller, Norbert Felber, Christian Pendl
100 Gbit/s authenticated encryption based on quantum key distribution. VLSI-SoC (2012)
Patrick Maechler, Christoph Studer, David E. Bellasi, Arian Maleki, Andreas Burg, Norbert Felber, Hubert Kaeslin, Richard G. Baraniuk
VLSI Design of Approximate Message Passing for Signal Restoration and Compressive Sensing. IEEE J. Emerg. Sel. Topics Circuits Syst. 2 (3) (2012)
Patrick Maechler, David E. Bellasi, Andreas Burg, Norbert Felber, Hubert Kaeslin, Christoph Studer
Sparsity-based real-time audio restoration. DASIP (2012)
Patrick Maechler, Norbert Felber, Hubert Kaeslin
Compressive sensing for WiFi-based passive bistatic radar. EUSIPCO (2012)
Michael Muehlberghuber, Christoph Keller, Frank K. Gürkaynak, Norbert Felber
FPGA-Based High-Speed Authenticated Encryption System. VLSI-SoC (Selected Papers) (2012)
Patrick Maechler, Norbert Felber, Andreas Peter Burg
Random sampling ADC for sparse spectrum sensing. EUSIPCO (2011)
Marc Simon Wegmueller, Michael Oberle, Norbert Felber, Niels Kuster, Wolfgang Fichtner
Signal Transmission by Galvanic Coupling Through the Human Body. IEEE Trans. Instrum. Meas. 59 (4) (2010)
Erich Wenger, Martin Feldhofer, Norbert Felber
Low-Resource Hardware Design of an Elliptic Curve Processor for Contactless Devices. WISA (2010)
Patrick Maechler, Pierre Greisen, Norbert Felber, Andreas Burg
Matching pursuit: Evaluation and implementatio for LTE channel estimation. ISCAS (2010)
Markus Wenk, Peter Luethi, Thomas Koch, Patrick Maechler, Norbert Felber, Wolfgang Fichtner, Michael Lerjen
Hardware Platform and Implementation of a Real-time Multi-user MIMO-OFDM Testbed. ISCAS (2009)
Markus Wenk, Peter Luethi, Thomas Koch, Patrick Maechler, Norbert Felber, Wolfgang Fichtner, Michael Lerjen
Live Demonstration: Hardware Platform and Implementation of a Real-time Multi-user MIMO-OFDM Testbed. ISCAS (2009)
Marc Simon Wegmueller, Sonja Huclova, Juerg Froehlich, Michael Oberle, Norbert Felber, Niels Kuster, Wolfgang Fichtner
Galvanic Coupling Enabling Wireless Implant Communications. IEEE Trans. Instrum. Meas. 58 (8) (2009)
Luca Henzen, Flavio Carbognani, Norbert Felber, Wolfgang Fichtner
Hardware evaluation of the stream cipher-based hash functions RadioGatún and irRUPT. DATE (2009)
Simon Heinzle, Olivier Saurer, Sebastian Axmann, Diego Browarnik, Andreas Schmidt, Flavio Carbognani, Peter Luethi, Norbert Felber, Markus H. Gross
A transform, lighting and setup ASIC for surface splatting. ISCAS (2008)
Daniel M. Hein, Johannes Wolkerstorfer, Norbert Felber
ECC Is Ready for RFID - A Proof in Silicon. Selected Areas in Cryptography (2008)
Peter Luethi, Markus Wenk, Thomas Koch, Wolfgang Fichtner, Michael Lerjen, Norbert Felber
Multi-user MIMO testbed. WINTECH (2008)
Luca Henzen, Flavio Carbognani, Norbert Felber, Wolfgang Fichtner
FPGA implementation of a 2G fibre channel link encryptor with authenticated encryption mode GCM. SoC (2008)
Flavio Carbognani, Felix Bürgin, Norbert Felber, Hubert Kaeslin, Wolfgang Fichtner
Transmission Gates Combined With Level-Restoring CMOS Gates Reduce Glitches in Low-Power Low-Frequency Multipliers. IEEE Trans. Very Large Scale Integr. Syst. 16 (7) (2008)
Peter Luethi, Christoph Studer, Sebastian Duetsch, Eugen Zgraggen, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner
Gram-Schmidt-based QR decomposition for MIMO detection: VLSI implementation and comparison. APCCAS (2008)
Stefan Lemsitzer, Johannes Wolkerstorfer, Norbert Felber, Matthias Braendli
Multi-gigabit GCM-AES Architecture Optimized for FPGAs. CHES (2007)
Simon Haene, Andreas Burg, Peter Luethi, Norbert Felber, Wolfgang Fichtner
FFT Processor for OFDM Channel Estimation. ISCAS (2007)
Marc Simon Wegmueller, Andreas Kuhn, Juerg Froehlich, Michael Oberle, Norbert Felber, Niels Kuster, Wolfgang Fichtner
An Attempt to Model the Human Body as a Communication Channel. IEEE Trans. Biomed. Eng. 54 (10) (2007)
Tim Weyrich, Simon Heinzle, Timo Aila, Daniel Bernhard Fasnacht, Stephan Oetiker, Mario Botsch, Cyril Flaig, Simon Mall, Kaspar Rohrer, Norbert Felber, Hubert Kaeslin, Markus H. Gross
A hardware architecture for surface splatting. ACM Trans. Graph. 26 (3) (2007)
C. Hess, Markus Wenk, Andreas Burg, Peter Luethi, Christoph Studer, Norbert Felber, Wolfgang Fichtner
Reduced-complexity mimo detector with close-to ml error rate performance. ACM Great Lakes Symposium on VLSI (2007)
Flavio Carbognani, Simon Haene, Manuel Arrigo, Claudio Pagnamenta, Felix Bürgin, Norbert Felber, Hubert Kaeslin, Wolfgang Fichtner
A 0.25 μm 0.92 mW per Mb/s Viterbi decoder featuring resonant clocking for ultra-low-power 54 Mb/s WLAN communication. CICC (2007)
Peter Luethi, Andreas Burg, Simon Haene, David Perels, Norbert Felber, Wolfgang Fichtner
VLSI Implementation of a High-Speed Iterative Sorted MMSE QR Decomposition. ISCAS (2007)
Markus Wenk, Martin Zellweger, Andreas Burg, Norbert Felber, Wolfgang Fichtner
K-best MIMO detection VLSI architectures achieving up to 424 Mbps. ISCAS (2006)
Flavio Carbognani, Felix Bürgin, Norbert Felber, Hubert Kaeslin, Wolfgang Fichtner
42% power savings through glitch-reducing clocking strategy in a hearing aid application. ISCAS (2006)
Simon Haene, Andreas Burg, David Perels, Peter Luethi, Norbert Felber, Wolfgang Fichtner
Silicon implementation of an MMSE-based soft demapper for MIMO-BICM. ISCAS (2006)
David Perels, Simon Haene, Andreas Burg, Peter Luethi, Norbert Felber, Wolfgang Fichtner
A Frame-Start Detector for a 4×4 MIMO-OFDM System. ICASSP (4) (2006)
Felix Bürgin, Flavio Carbognani, Martin Hediger, Hektor Meier, Robert Meyer-Piening, Rafael Santschi, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner
Low-power architectural trade-offs in a VLSI implementation of an adaptive hearing aid algorithm. DAC (2006)
Flavio Carbognani, Felix Bürgin, Norbert Felber, Hubert Kaeslin, Wolfgang Fichtner
Two-phase resonant clocking for ultra-low-power hearing aid applications. DATE (2006)
Frank K. Gürkaynak, Stephan Oetiker, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner
Design Challenges for a Differential-Power-Analysis Aware GALS-based AES Crypto ASIC. Electron. Notes Theor. Comput. Sci. 146 (2) (2006)
Andreas Burg, Simon Haene, David Perels, Peter Luethi, Norbert Felber, Wolfgang Fichtner
Algorithm and VLSI architecture for linear MMSE detection in MIMO-OFDM systems. ISCAS (2006)
Frank K. Gürkaynak, Stephan Oetiker, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner
GALS at ETH Zurich: Success or Failure. ASYNC (2006)
David Perels, Simon Haene, Peter Luethi, Andreas Peter Burg, Norbert Felber, Wolfgang Fichtner, Helmut Bölcskei
ASIC implementation of a MIMO-OFDM transceiver for 192 Mbps WLANs. ESSCIRC (2005)
Flavio Carbognani, Felix Bürgin, Luca Henzen, Herbert Koch, Hovig Magdassian, Christoph Pedretti, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner
45-μW DSP VLSI implementation of an adaptive directional microphone for hearing aids. ECCTD (2005)
Frank K. Gürkaynak, Stephan Oetiker, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner
Improving DPA security by using globally-asynchronous locally-synchronous systems. ESSCIRC (2005)
Flavio Carbognani, Felix Bürgin, Norbert Felber, Hubert Kaeslin, Wolfgang Fichtner
Two-Phase Clocking and a New Latch Design for Low-Power Portable Applications. PATMOS (2005)
Norbert Pramstaller, Frank K. Gürkaynak, Simon Haene, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner
Towards an AES crypto-chip resistant to differential power analysis. ESSCIRC (2004)
Andreas Burg, Markus Wenk, Martin Zellweger, Marc Simon Wegmueller, Norbert Felber, Wolfgang Fichtner
VLSI implementation of the sphere decoding algorithm. ESSCIRC (2004)
Frank K. Gürkaynak, Andreas Burg, Norbert Felber, Wolfgang Fichtner, D. Gasser, Franco Hug, Hubert Kaeslin
A 2 Gb/s balanced AES crypto-chip implementation. ACM Great Lakes Symposium on VLSI (2004)
Andreas Burg, Norbert Felber, Wolfgang Fichtner
A 50 Mbps 4×4 maximum likelihood decoder for multiple-input multiple-output systems with QPSK modulation. ICECS (2003)
Jürgen Wassner, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner
Waveform coding for low-power digital filtering of speech data. IEEE Trans. Signal Process. 51 (6) (2003)
Thomas Villiger, Stephan Oetiker, Frank K. Gürkaynak, Norbert Felber, Hubert Kaeslin, Wolfgang Fichtner
A Functional Test Methodology for Globally-Asynchronous Locally-Synchronous Systems. ASYNC (2002)
Manfred Stadler, Markus Thalmann, Thomas Röwer, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner
Design and Verification of a Stack Processor Virtual Component. IEEE Micro 21 (2) (2001)
Jan Thalheim, Norbert Felber, Wolfgang Fichtner
A new approach for controlling series-connected IGBT modules. ISCAS (3) (2001)
Daniel Doswald, Jürg Häfliger, Patrick Blessing, Norbert Felber, Peter Niederer, Wolfgang Fichtner
A 30-frames/s megapixel real-time CMOS image processor. IEEE J. Solid State Circuits 35 (11) (2000)
Thomas Roewer, Manfred Stadler, Markus Thalmann, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner
A new paradigm for very flexible SONET/SDH IP-modules. CICC (2000)
Manfred Stadler, Thomas Röwer, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner, Markus Thalmann
Functional verification of intellectual properties (IP): a simulation-based solution for an application-specific instruction-set processor. ITC (1999)
Manfred Stadler, Markus Thalmann, Thomas Röwer, Norbert Felber, Wolfgang Fichtner
An embedded stack microprocessor for SDH telecommunication applications. CICC (1998)
Reto Zimmermann, Andreas Curiger, Heinz Bonnenberg, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner
A 177 Mb/s VLSI implementation of the International Data Encryption Algorithm. IEEE J. Solid State Circuits 29 (3) (1994)
H. Bonnenberg, Andreas Curiger, Norbert Felber, Hubert Kaeslin, R. Zimmermann, Wolfgang Fichtner
VINCI: Secure Test of a VLSI High-Speed Encryption System. ITC (1993)
H. Bonnenberg, Andreas Curiger, Norbert Felber, Hubert Kaeslin, Xuejia Lai
VLSI Implementation of a New Block Cipher. ICCD (1991)