The impact of transistor sizing on power efficiency in submicron CMOS circuits.
Robert RogenmoserHubert KaeslinPublished in: IEEE J. Solid State Circuits (1997)
Keyphrases
- power dissipation
- low power
- vlsi circuits
- power consumption
- high speed
- mixed signal
- power reduction
- cmos technology
- circuit design
- chip design
- low cost
- logic circuits
- delay insensitive
- floating gate
- digital signal processing
- analog vlsi
- single chip
- power management
- focal plane
- electron beam
- highly efficient
- infrared
- flip flops
- image processing
- image sensor
- finite state machines
- signal processing
- computational complexity