Fuminori Kobayashi

Publication Activity (10 Years)

Years Active: 1987-2022
Publications (10 Years): 2

Top Topics

Data Conversion

Digital Computer

Top Venues

Publications

Fuminori Kobayashi
Analog Correlator by a Dynamically-Reconfigured Switched-Capacitor Circuit. ISCAS (2022)
Shinya Furukawa, Ili Shairah Abdul Halim, Minoru Watanabe, Fuminori Kobayashi
Direct optical communication on an optically reconfigurable gate array. FGCT (2016)
Nordinah Ismail, Fuminori Kobayashi, Manabu Inoue
Integrally accurate resolver-to-digital converter (RDC). ASCC (2015)
Takayuki Mabuchi, Minoru Watanabe, Akifumi Ogiwara, Fuminori Kobayashi
Optically reconflgurable gate array with a polymer-dispersed liquid crystal holographic memory. AHS (2011)
Hidekazu Machida, Michinobu Kambara, Kouta Tanaka, Fuminori Kobayashi
A motor speed control system using a hybrid of dual-loop PLL and feed-forward. AMC (2010)
Fuminori Kobayashi, Yuhta Egashira, Hitoshi Kondoh
A PLL configuration for reducing both incoming and inherent jitters. ICECS (2009)
Fuminori Kobayashi, Yasuyuki Morikawa, Minoru Watanabe
MISC: Mono Instruction-Set Computer based on Dynamic Reconfiguration - a 6502 Perspective. ERSA (2008)
Yutaka Nakanishi, Fuminori Kobayashi, Hitoshi Kondoh
Low-jitter PLL by interpolate compensation. APCCAS (2008)
Minoru Watanabe, Takenori Shiki, Fuminori Kobayashi
272 Gate Count Optically Differential Reconfigurable Gate Array VLSI. ERSA (2007)
Rio Miyazaki, Minoru Watanabe, Fuminori Kobayashi
A multi-context holographic memory recording system for Optically Reconfigurable Gate Arrays. IPDPS (2007)
Minoru Watanabe, Fuminori Kobayashi
Holographic memory reconfigurable VLSI. ISCAS (2007)
Minoru Watanabe, Fuminori Kobayashi
A 0.35um CMOS 1, 632-gate-count Zero-Overhead Dynamic Optically Reconfigurable Gate Array VLSI. ASP-DAC (2007)
Minoru Watanabe, Fuminori Kobayashi
Shield Effect Analysis for a Gate Array on An Optically Reconfigurable Gate Array. ERSA (2006)
Minoru Watanabe, Fuminori Kobayashi
Logic Synthesis and Place-and-Route Environment for ORGAs. ERSA (2006)
Minoru Watanabe, Fuminori Kobayashi
Optically Reconfigurable Gate Arrays vs. ASICs. APCCAS (2006)
Minoru Watanabe, Fuminori Kobayashi
Power consumption advantage of a dynamic optically reconfigurable gate array. IPDPS (2006)
Minoru Watanabe, Mototsugu Miyano, Fuminori Kobayashi
Differential Reconfiguration Architecture suitable for a Holographic Memory. ERSA (2006)
Minoru Watanabe, Mototsugu Miyano, Fuminori Kobayashi
An optically differential reconfigurable gate array with a holographic memory. IPDPS (2006)
Minoru Watanabe, Fuminori Kobayashi
A 1, 632 Gate-Count Zero-Overhead Dynamic Optically Reconfigurable Gate Array VLSI. ARC (2006)
Minoru Watanabe, Fuminori Kobayashi
A Reconfiguration Speed Adjustment Technique for ORGAs with a Holographic Memory. FPL (2006)
Minoru Watanabe, Fuminori Kobayashi
A 476-gate-count dynamic optically reconfigurable gate array VLSI chip in a standard 0.35 micrometer CMOS technology. ASP-DAC (2006)
Minoru Watanabe, Fuminori Kobayashi
A Zero-Overhead Dynamic Optically Reconfigurable Gate Array. FPT (2005)
Minoru Watanabe, Fuminori Kobayashi
A 16, 000-gate-count optically reconfigurable gate array in a standard 0.35µm CMOS technology. ISCAS (2) (2005)
Mototsugu Miyano, Minoru Watanabe, Fuminori Kobayashi
Rapid Reconfiguration of an Optically Differential Reconfigurable Gate Array with Pulse Lasers. FPT (2005)
Minoru Watanabe, Fuminori Kobayashi
An Improved Dynamic Optically Reconfigurable Gate Array. ISVLSI (2005)
Mototsugu Miyano, Minoru Watanabe, Fuminori Kobayashi
Optically Differential Reconfigurable Gate Array Using an Optical System with VCSELs. ISVLSI (2005)
Minoru Watanabe, Fuminori Kobayashi
An Optically Differential Reconfigurable Gate Array VLSI Chip with a Dynamic Reconfiguration Circuit. IPDPS (2005)
Minoru Watanabe, Fuminori Kobayashi
A High-Density Optically Reconfigurable Gate Array Using Dynamic Method. FPL (2004)
Minoru Watanabe, Fuminori Kobayashi
An Optically Differential Reconfigurable Gate Array with a partial reconfiguration optical system and its power consumption estimation. VLSI Design (2004)
Minoru Watanabe, Fuminori Kobayashi
Testing Method for Optical Connections Using Gate Array Structure in ORGAs. ERSA (2004)
Minoru Watanabe, Fuminori Kobayashi
An optically differential reconfigurable gate array using a 0.18 μm CMOS process. SoCC (2004)
Minoru Watanabe, Fuminori Kobayashi
Timing Analysis of an Optically Differential Reconfigurable Gate Array for Dynamically Reconfigurable Processors. ERSA (2004)
Minoru Watanabe, Fuminori Kobayashi
An Optically Differential Reconfigurable Gate Array with a Dynamic Reconfiguration Circuit. IPDPS (2003)
Minoru Watanabe, Fuminori Kobayashi
An optically differential reconfigurable gate array and its power consumption estimation. FPT (2002)
Fuminori Kobayashi, Masayuki Haratsu, Masateru Yabumoto, Michio Nakano
Efficient digital techniques for implementing a class of fast phase-locked loops (PLL's). IEEE Trans. Ind. Electron. 43 (6) (1996)
Fuminori Kobayashi, Masayuki Haratsu
A Digital PLL with Finite Impulse Responses. ISCAS (1995)
Yoichi Kimura, Ryoji Mukai, Fuminori Kobayashi, Masaru Kobayashi
Interpolative variable-speed repetitive control and its application to a deburring robot with cutting load control. Adv. Robotics 7 (1) (1992)
Fuminori Kobayashi, Hiroshi Suzuki
Time-varying signals analysis using squared analytic signals. ICASSP (1987)