An optically differential reconfigurable gate array with a holographic memory.

Minoru Watanabe Mototsugu Miyano Fuminori Kobayashi

Published in: IPDPS (2006)

Keyphrases

gate array
low power
low cost
logic circuits
general purpose
reconfigurable architecture
hardware implementation
power consumption
machine learning
digital signal
information retrieval
high speed
digital signal processing
multi objective evolutionary