Timing Analysis of an Optically Differential Reconfigurable Gate Array for Dynamically Reconfigurable Processors.
Minoru WatanabeFuminori KobayashiPublished in: ERSA (2004)
Keyphrases
- gate array
- low power
- low cost
- parallel processing
- power reduction
- parallel algorithm
- logic circuits
- power consumption
- reconfigurable architecture
- heterogeneous computing
- high speed
- fine grain
- parallel computation
- general purpose
- multi objective evolutionary
- multiprocessor systems
- hardware implementation
- single processor
- parallel computing
- shared memory
- processing elements
- parallel architecture
- high end
- distributed memory
- embedded processors
- high performance computing