A 0.35um CMOS 1, 632-gate-count Zero-Overhead Dynamic Optically Reconfigurable Gate Array VLSI.

Minoru Watanabe Fuminori Kobayashi

Published in: ASP-DAC (2007)

Keyphrases

gate array
low power
low cost
logic circuits
cmos technology
pattern recognition
query processing
high speed
dynamic environments
power consumption
design methodology
multiple input
nano scale