A 16, 000-gate-count optically reconfigurable gate array in a standard 0.35µm CMOS technology.

Minoru Watanabe Fuminori Kobayashi

Published in: ISCAS (2) (2005)

Keyphrases

cmos technology
low power
gate array
low cost
power consumption
high speed
spl times
low voltage
parallel processing
logic circuits
mixed signal
image sensor
power dissipation
digital signal processing
real time
hardware implementation
computer vision