An optically differential reconfigurable gate array using a 0.18 μm CMOS process.

Minoru Watanabe Fuminori Kobayashi

Published in: SoCC (2004)

Keyphrases

gate array
low power
low cost
logic circuits
general purpose
reconfigurable architecture
power consumption
multi objective evolutionary
field programmable gate array
hardware implementation
pattern recognition
image processing
database
high speed
neural network
data sets
heterogeneous computing
real time