Tests for small gate delay faults in combinational circuits and a test generation method.
Hiroshi TakahashiTakashi WatanabeToshiyuki MatsunagaYuzo TakamatsuPublished in: Systems and Computers in Japan (1997)
Keyphrases
- generation method
- built in self test
- test cases
- test data
- test suite
- test generation
- statistical tests
- multiple choice
- post hoc
- asynchronous circuits
- mutation testing
- cmos technology
- logic circuits
- test sequences
- power dissipation
- delay insensitive
- digital circuits
- expert systems
- logic synthesis
- item response theory
- genetic algorithm
- fault diagnosis
- software testing
- power consumption
- integrated circuit