NEST: A Non-Enumerative Test Generation Method for Path Delay Faults in Combinational Circuits.
Irith PomeranzSudhakar M. ReddyPrasanti UppaluriPublished in: DAC (1993)
Keyphrases
- generation method
- built in self test
- test cases
- integrated circuit
- fault diagnosis
- logic circuits
- test data
- high speed
- power dissipation
- optimal path
- mutation testing
- fault models
- diagnostic tests
- multiple paths
- test sequences
- path length
- model based diagnosis
- endpoints
- statistical tests
- integer programming
- shortest path