Suchismita Roy

Publication Activity (10 Years)

Years Active: 2005-2024
Publications (10 Years): 30

Top Topics

Top Venues

J. Circuits Syst. Comput.

Biomed. Signal Process. Control.

Publications

Anindan Mondal, Archisman Ghosh, Shubrojyoti Karmakar, Mahabub Hasan Mahalat, Suchismita Roy, Bibhash Sen
Identification of Hardware Trojan in Gate-Level Netlist. J. Circuits Syst. Comput. 33 (9) (2024)
Sunanda Das, Abhishek Kesarwani, Mamata Dalui, Dakshina Ranjan Kisku, Bibhash Sen, Suchismita Roy, Anupam Basu
Smartphone-based non-invasive haemoglobin level estimation by analyzing nail pallor. Biomed. Signal Process. Control. 85 (2023)
Anindan Mondal, Shubrojyoti Karmakar, Mahabub Hasan Mahalat, Suchismita Roy, Bibhash Sen, Anupam Chattopadhyay
Hardware Trojan Detection using Transition Probability with Minimal Test Vectors. ACM Trans. Embed. Comput. Syst. 22 (1) (2023)
Anindan Mondal, Debasish Kalita, Archisman Ghosh, Suchismita Roy, Bibhash Sen
Toward the Generation of Test Vectors for the Detection of Hardware Trojan Targeting Effective Switching Activity. ACM J. Emerg. Technol. Comput. Syst. 19 (4) (2023)
Abhishek Kesarwani, Sunanda Das, Mamata Dalui, Dakshina Ranjan Kisku, Bibhash Sen, Suchismita Roy, Anupam Basu
Non-invasive anaemia detection by examining palm pallor: A smartphone-based approach. Biomed. Signal Process. Control. 79 (Part) (2023)
Suchandra Banerjee, Suchismita Roy
Power aware floorplanning in multiple supply voltage domain. Int. J. Circuit Theory Appl. 50 (2) (2022)
Sudeshna Kundu, Suchismita Roy, Shyamapada Mukherjee
Congestion-Aware Rectilinear Steiner Tree Construction Using PB-SAT. J. Circuits Syst. Comput. 31 (9) (2022)
Sourav Roy, Dipnarayan Das, Anindan Mondal, Mahabub Hasan Mahalat, Suchismita Roy, Bibhash Sen
PUF based Lightweight Authentication and Key Exchange Protocol for IoT. SECRYPT (2021)
Anindan Mondal, Rajesh Kumar Biswal, Mahabub Hasan Mahalat, Suchismita Roy, Bibhash Sen
Hardware Trojan Free Netlist Identification: A Clustering Approach. J. Electron. Test. 37 (3) (2021)
Suchandra Banerjee, Suchismita Roy
Thermal-Driven Floorplanning for Fixed Outline Layouts. J. Circuits Syst. Comput. 30 (5) (2021)
Sudeshna Kundu, Suchismita Roy, Shyamapada Mukherjee
Rectilinear Steiner Tree Construction Techniques Using PB-SAT-Based Methodology. J. Circuits Syst. Comput. 29 (4) (2020)
Sanjib Sadhu, Xiaozhou He, Sasanka Roy, Subhas C. Nandy, Suchismita Roy
Corrigendum to: "Linear time algorithm to cover and hit a set of line segments optimally by two axis-parallel squares" [Theor. Comput. Sci. 769 (2019) 63-74]. Theor. Comput. Sci. 806 (2020)
Sanjib Sadhu, Sasanka Roy, Soumen Nandi, Subhas C. Nandy, Suchismita Roy
Efficient Algorithm for Computing the Triangle Maximizing the Length of Its Smallest Side Inside a Convex Polygon. Int. J. Found. Comput. Sci. 31 (4) (2020)
Sanjib Sadhu, Xiaozhou He, Sasanka Roy, Subhas C. Nandy, Suchismita Roy
Corrigendum to: "Linear time algorithm to cover and hit a set of line segments optimally by two axis-parallel squares", Theoretical Computer Science 769 (2019) 63-74. CoRR (2019)
Anindan Mondal, Mahabub Hasan Mahalat, Suraj Mandal, Suchismita Roy, Bibhash Sen
A Novel Test Vector Generation Method for Hardware Trojan Detection. SoCC (2019)
Shukla Banik, Suchismita Roy, Bibhash Sen
Application-Dependent Testing of FPGA Interconnect Network. IEEE Trans. Very Large Scale Integr. Syst. 27 (10) (2019)
Shukla Banik, Suchismita Roy, Bibhash Sen
An Integrated Framework for Application Independent Testing of FPGA Interconnect. J. Electron. Test. 35 (5) (2019)
Sanjib Sadhu, Sasanka Roy, Subhas C. Nandy, Suchismita Roy
Linear time algorithm to cover and hit a set of line segments optimally by two axis-parallel squares. Theor. Comput. Sci. 769 (2019)
Khushbu Chandrakar, Suchismita Roy
A SAT-Based Methodology for Effective Clock Gating for Power Minimization. J. Circuits Syst. Comput. 28 (1) (2019)
Shukla Banik, Suchismita Roy, Bibhash Sen
Test Configuration Generation for Different FPGA Architectures for Application Independent Testing. VLSI Design (2019)
Khushbu Chandrakar, Sudeshna Kundu, Suchismita Roy
Power Optimization Techniques for High-Level Designs Using Multiple Voltage Components for Low Power Consumption. J. Low Power Electron. 14 (2) (2018)
Anindan Mondal, Mahabub Hasan Mahalat, Anudeep Reddy Medapati, Suchismita Roy, Bibhash Sen
XOR based Methodology to Detect Hardware Trojan utilizing the Transition Probability. ISED (2018)
Suchandra Banerjee, Anand Ratna, Suchismita Roy
Satisfiability Modulo Theory based Methodology for Floorplanning in VLSI Circuits. CoRR (2017)
Shyamapada Mukherjee, Suchismita Roy
Via-Aware Dogleg Routing Using Boolean Satisfiability. J. Circuits Syst. Comput. 26 (4) (2017)
Sanjib Sadhu, Sasanka Roy, Subhas C. Nandy, Suchismita Roy
A linear time algorithm to cover and hit a set of line segments optimally by two axis-parallel squares. CoRR (2017)
Sanjib Sadhu, Sasanka Roy, Soumen Nandi, Subhas C. Nandy, Suchismita Roy
Computing the Triangle Maximizing the Length of Its Smallest Side Inside a Convex Polygon. ICCSA (2) (2017)
Sudeshna Kundu, Suchismita Roy, Shyamapada Mukherjee
K-nearest neighbour (KNN) approach using SAT based technique for rectilinear steiner tree construction. ISED (2017)
Sanjib Sadhu, Sasanka Roy, Subhas C. Nandy, Suchismita Roy
Optimal Covering and Hitting of Line Segments by Two Axis-Parallel Squares. COCOON (2017)
Suchandra Banerjee, Anand Ratna, Suchismita Roy
Satisfiability modulo theory based methodology for floorplanning in VLSI circuits. ISED (2016)
Shyamapada Mukherjee, Suchismita Roy
Nearly-2-SAT Solutions for Segmented-Channel Routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35 (1) (2016)
Shyamapada Mukherjee, Suchismita Roy
SAT based solutions for detailed routing of island style FPGA architectures. Microelectron. J. 46 (8) (2015)
Shyamapada Mukherjee, Suchismita Roy
Multi terminal net routing for island style FPGAs using nearly-2-SAT computation. VDAT (2015)
Shyamapada Mukherjee, Jibesh Patra, Suchismita Roy
Congestion Balancing Global Router. VDAT (2013)
Khushbu Chandrakar, Suchismita Roy
SAT based low power binding to reduce switching activity. IC3 (2013)
Suchismita Roy, P. P. Chakrabarti, Pallab Dasgupta
SAT based timing analysis for fixed and rise/fall gate delay models. Integr. 45 (4) (2012)
Suchismita Roy, P. P. Chakrabarti, Pallab Dasgupta
Bounded delay timing analysis and power estimation using SAT. Microelectron. J. 41 (5) (2010)
Suchismita Roy, P. P. Chakrabarti, Pallab Dasgupta
Satisfiability Models for Maximum Transition Power. IEEE Trans. Very Large Scale Integr. Syst. 16 (8) (2008)
Suchismita Roy, P. P. Chakrabarti, Pallab Dasgupta
Event propagation for accurate circuit delay calculation using SAT. ACM Trans. Design Autom. Electr. Syst. 12 (3) (2007)
Suchismita Roy, P. P. Chakrabarti, Pallab Dasgupta
Bounded Delay Timing Analysis Using Boolean Satisfiability. VLSI Design (2007)
Suchismita Roy, Sayantan Das, Prasenjit Basu, Pallab Dasgupta, Partha Pratim Chakrabarti
SAT based solutions for consistency problems in formal property specifications for open systems. ICCAD (2005)