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Khushbu Chandrakar
Publication Activity (10 Years)
Years Active: 2013-2019
Publications (10 Years): 2
Top Topics
Logic Circuits
Delay Insensitive
Answer Set Programming
Low Power Consumption
Top Venues
J. Low Power Electron.
IC3
J. Circuits Syst. Comput.
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Publications
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Khushbu Chandrakar
,
Suchismita Roy
A SAT-Based Methodology for Effective Clock Gating for Power Minimization.
J. Circuits Syst. Comput.
28 (1) (2019)
Khushbu Chandrakar
,
Sudeshna Kundu
,
Suchismita Roy
Power Optimization Techniques for High-Level Designs Using Multiple Voltage Components for Low Power Consumption.
J. Low Power Electron.
14 (2) (2018)
Khushbu Chandrakar
,
Suchismita Roy
SAT based low power binding to reduce switching activity.
IC3
(2013)