Bounded Delay Timing Analysis Using Boolean Satisfiability.
Suchismita RoyP. P. ChakrabartiPallab DasguptaPublished in: VLSI Design (2007)
Keyphrases
- boolean satisfiability
- sat solvers
- boolean optimization
- branch and bound algorithm
- sat solving
- randomly generated
- sat problem
- integer linear programming
- probabilistic planning
- symmetry breaking
- max sat
- maximum satisfiability
- lower bound
- sat instances
- combinatorial problems
- random sat instances
- phase transition
- boolean formula
- branch and bound
- constraint programming
- simulated annealing
- np hard