Rino Micheloni

Publication Activity (10 Years)

Years Active: 2000-2023
Publications (10 Years): 17

Top Topics

Design Space Exploration

Top Venues

IEEE Trans. Circuits Syst. II Express Briefs

Publications

Milan Pesic, Bastien Beltrando, Tommaso Rollo, Cristian Zambelli, Andrea Padovani, Rino Micheloni, Rita Maji, Lisa Enman, Mark Saly, Yang Ho Bae, Jung Bae Kim, Dong Kil Yim, Luca Larcher
Insights into device and material origins and physical mechanisms behind cross temperature in 3D NAND. IRPS (2023)
Michela Borghesi, Cristian Zambelli, Rino Micheloni, Stefano Bonnini
Modeling 3D NAND Flash with Nonparametric Inference on Regression Coefficients for Reliable Solid-State Storage. Future Internet 15 (10) (2023)
Giada Minghini, Armando Ugo Cavallo, Andrea Miola, Valentina Sisini, Enrico Calore, Francesca Fortini, Rino Micheloni, Paola Rizzo, Sebastiano Fabio Schifano, Francesco Vieceli Dalla Sega, Cristian Zambelli
An HPC Pipeline for Calcium Quantification of Aortic Root From Contrast-Enhanced CCT Scans. IEEE Access 11 (2023)
Mohammad Rowshan, Emanuele Viterbo, Rino Micheloni, Alessia Marelli
Logarithmic Non-uniform Quantization for List Decoding of Polar Codes. CCWC (2021)
Viduranga Bandara Wijekoon, Emanuele Viterbo, Yi Hong, Rino Micheloni, Alessia Marelli
A Novel Graph Expansion and a Decoding Algorithm for NB-LDPC Codes. IEEE Trans. Commun. 68 (3) (2020)
Lorenzo Zuolo, Cristian Zambelli, Alessia Marelli, Rino Micheloni, Piero Olivo
LDPC Soft Decoding with Improved Performance in 1X-2X MLC and TLC NAND Flash-Based Solid State Drives. IEEE Trans. Emerg. Top. Comput. 7 (3) (2019)
Shuiyin Liu, Yi Hong, Emanuele Viterbo, Alessia Marelli, Rino Micheloni
Efficient Decoding of Low Density Lattice Codes. IEEE Wirel. Commun. Lett. 8 (4) (2019)
Cristian Zambelli, Riccardo Bertaggia, Lorenzo Zuolo, Rino Micheloni, Piero Olivo
Enabling Computational Storage Through FPGA Neural Network Accelerator for Enterprise SSD. IEEE Trans. Circuits Syst. II Express Briefs (10) (2019)
Viduranga Bandara Wijekoon, Shuiyin Liu, Emanuele Viterbo, Yi Hong, Rino Micheloni, Alessia Marelli
Coset Probability Based Majority-logic Decoding for Non-binary LDPC Codes. ITW (2019)
Shuiyin Liu, Yi Hong, Emanuele Viterbo, Alessia Marelli, Rino Micheloni
Fast Decoding of Low Density Lattice Codes. CoRR (2018)
Rino Micheloni
Solid-State Drive (SSD): A Nonvolatile Storage System. Proc. IEEE 105 (4) (2017)
Lorenzo Zuolo, Cristian Zambelli, Rino Micheloni, Piero Olivo
Solid-State Drives: Memory Driven Design Methodologies for Optimal Performance. Proc. IEEE 105 (9) (2017)
Rino Micheloni, Piero Olivo
Solid-State Drives (SSDs) [Scanning the Issue]. Proc. IEEE 105 (9) (2017)
Rino Micheloni, Seiichi Aritome, Luca Crippa
Array Architectures for 3-D NAND Flash Memories. Proc. IEEE 105 (9) (2017)
Rino Micheloni, Luca Crippa, Cristian Zambelli, Piero Olivo
Architectural and Integration Options for 3D NAND Flash Memories. Comput. 6 (3) (2017)
Lorenzo Zuolo, Cristian Zambelli, Rino Micheloni, Marco Indaco, Stefano Di Carlo, Paolo Prinetto, Davide Bertozzi, Piero Olivo
SSDExplorer: A Virtual Platform for Performance/Reliability-Oriented Fine-Grained Design Space Exploration of Solid State Drives. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34 (10) (2015)
Lorenzo Zuolo, Cristian Zambelli, Rino Micheloni, Stephen Bates, Piero Olivo
Design space exploration of latency and bandwidth in RRAM-based solid state drives. NVMTS (2015)
Kai Zhao, Jiangpeng Li, Jun Ma, Rino Micheloni, Tong Zhang
Overclocking nand Flash Memory I/O Link in LDPC-Based SSDs. IEEE Trans. Circuits Syst. II Express Briefs (11) (2014)
Lorenzo Zuolo, Cristian Zambelli, Rino Micheloni, Salvatore Galfano, Marco Indaco, Stefano Di Carlo, Paolo Prinetto, Piero Olivo, Davide Bertozzi
SSDExplorer: A virtual platform for fine-grained design space exploration of Solid State Drives. DATE (2014)
Tong Zhang, Rino Micheloni, Guoyan Zhang, Zhaoran Rena Huang, James Jian-Qiang Lu
3-D Data Storage, Power Delivery, and RF/Optical Transceiver - Case Studies of 3-D Integration From System Design Perspectives. Proc. IEEE 97 (1) (2009)
Rino Micheloni, Massimiliano Picca, Stefano Amato, Helmut Schwalm, Michael Scheppler, Stefano Commodaro
Non-Volatile Memories for Removable Media. Proc. IEEE 97 (1) (2009)
Rino Micheloni, R. Ravasio, Alessia Marelli, E. Alice, V. Altieri, A. Bovino, Luca Crippa, E. Di Martino, L. D'Onofrio, A. Gambardella, E. Grillea, G. Guerra, D. Kim, C. Missiroli, Ilaria Motta, A. Prisco, Giancarlo Ragone, M. Romano, Miriam Sangalli, P. Sauro, Marco Scotti, S. Won
A 4Gb 2b/cell NAND Flash Memory with Embedded 5b BCH ECC for 36MB/s System Read Throughput. ISSCC (2006)
Alessandro Cabrini, Rino Micheloni, Osama Khouri, Stefano Gregori, Guido Torelli
High input range sense comparator for multilevel Flash memories. ISCAS (2) (2004)
Rino Micheloni, Luca Crippa, Miriam Sangalli, Giovanni Campardo
The flash memory read path: building blocks and critical aspects. Proc. IEEE 91 (4) (2003)
Ilaria Motta, Giancarlo Ragone, Osama Khouri, Guido Torelli, Rino Micheloni
High-voltage management in single-supply CHE NOR-type flash memories. Proc. IEEE 91 (4) (2003)
Osama Khouri, Stefano Gregori, Dario Soltesz, Guido Torelli, Rino Micheloni
Low Output Resistance Charge Pump for Flash Memory Programming. MTDT (2001)
Stefano Gregori, Guido Torelli, Osama Khouri, Rino Micheloni
An Error Control Code Scheme for Multilevel Flash Memories. MTDT (2001)
Rino Micheloni, Ilaria Motta, Osama Khouri, Guido Torelli
Stand-by low-power architecture in a 3 V-only 2-bit/cell 64-Mbit flash memory. ICECS (2001)
Andrea Pierin, Stefano Gregori, Osama Khouri, Rino Micheloni, Guido Torelli
High-speed low-power sense comparator for multilevel flash memories. ICECS (2000)
Osama Khouri, Rino Micheloni, Andrea Sacco, Giovanni Campardo, Guido Torelli
Program word-line voltage generator for multilevel flash memories. ICECS (2000)
Rino Micheloni, Matteo Zammattio, Giovanni Campardo, Osama Khouri, Guido Torelli
Hierarchical Sector Biasing Organization for Flash Memories. MTDT (2000)
Osama Khouri, Rino Micheloni, Stefano Gregori, Guido Torelli
Fast Voltage Regulator for Multilevel Flash Memories. MTDT (2000)
Giovanni Campardo, Rino Micheloni, Stefano Commodaro, Emilio Yero, Matteo Zammattio, Sabina Mognoni, Andrea Sacco, Massimiliano Picca, Alessandro Manstretta, Marco Scotti, Ilaria Motta, C. Golla, Andrea Pierin, Roberto Bez, Alessandro Grossi, Alberto Modelli, Angelo Visconti, Osama Khouri, Guido Torelli
3-V-only 50-MHz 64-Mb 2-b/cell CHE NOR flash memory. IEEE J. Solid State Circuits 35 (11) (2000)
Stefano Gregori, Pietro Ferrari, Rino Micheloni, Guido Torelli
Construction of polyvalent error control codes for multilevel memories. ICECS (2000)