Marius Strum

Publication Activity (10 Years)

Years Active: 1998-2015
Publications (10 Years): 0

Top Topics

Formal Treatment

Protocol Specification

Artificial Immune Algorithm

Hardware Designs

Top Venues

J. Electron. Test.

Publications

Raul Acosta Hernandez, Marius Strum, Jiang Chau Wang
Transformations on the FSMD of the RTL code with combinational logic statements for equivalence checking of HLS. LATS (2015)
Carlos Ivan Castro Marquez, Marius Strum, Jiang Chau Wang
A Unified Sequential Equivalence Checking Methodology to Verify RTL Designs with High-Level Functional and Protocol Specification Models. J. Electron. Test. 31 (3) (2015)
Martha Johanna Sepúlveda, Guy Gogniat, Daniel Florez, Jean-Philippe Diguet, Ricardo Pires, Marius Strum
TSV protection: Towards secure 3D-MPSoC. LASCAS (2015)
Jonas Gomes Filho, Marius Strum, Jiang Chau Wang
Using Genetic Algorithms for Hardware Core Placement and Mapping in NoC-Based Reconfigurable Systems. Int. J. Reconfigurable Comput. 2015 (2015)
Martha Johanna Sepúlveda, Jean-Philippe Diguet, Marius Strum, Guy Gogniat
NoC-Based Protection for SoC Time-Driven Attacks. IEEE Embed. Syst. Lett. 7 (1) (2015)
Carlos Ivan Castro Marquez, Marius Strum, Jiang Chau Wang
A unified sequential equivalence checking approach to verify high-level functionality and protocol specification implementations in RTL designs. LATW (2014)
Johanna Sepúlveda, Guy Gogniat, Daniel Florez, Jean-Philippe Diguet, César Pedraza, Marius Strum
3D-LeukoNoC: A dynamic NoC protection. ReConFig (2014)
Johanna Sepúlveda, Guy Gogniat, Daniel Florez, Jean-Philippe Diguet, Cesar A. Zeferino, Marius Strum
Elastic security zones for NoC-based 3D-MPSoCs. ICECS (2014)
Johanna Sepúlveda, Guy Gogniat, Ricardo Pires, César Pedraza, Wang Jiang Chau, Marius Strum
QoS 3D-HoC hybrid-on-chip communication structure for dynamic 3D-MPSoCs. LASCAS (2013)
Johanna Sepúlveda, Guy Gogniat, Ricardo Pires, Jiang Chau Wang, Marius Strum
Security-enhanced 3D communication structure for dynamic 3D-MPSoCs protection. SBCCI (2013)
Jonas Gomes Filho, Marius Strum, Wang Jiang Chau
A strategy for mapping reconfigurable cores in NoCs. LASCAS (2013)
Edgar Leonardo Romero, Marius Strum, Jiang Chau Wang
Manipulation of Training Sets for Improving Data Mining Coverage-Driven Verification. J. Electron. Test. 29 (2) (2013)
Carlos Ivan Castro Marquez, Marius Strum, Jiang Chau Wang
Functional verification of complete sequential behaviors: A formal treatment of discrepancies between system-level and RTL descriptions. IDT (2013)
Johanna Sepúlveda, Guy Gogniat, Ricardo Pires, Jiang Chau Wang, Marius Strum
An evolutive approach for designing thermal and performance-aware heterogeneous 3D-NoCs. SBCCI (2013)
Jean-Philippe Diguet, Marius Strum, Nicolas Le Griguer, Lydie Caetano, Martha Johanna Sepúlveda
Scalable NoC-based architecture of neural coding for new efficient associative memories. CODES+ISSS (2013)
Martha Johanna Sepúlveda, Guy Gogniat, Daniel Mauricio Sepúlveda, Ricardo Pires, Jiang Chau Wang, Marius Strum
3DMIA: a multi-objective artificial immune algorithm for 3D-MPSoC multi-application 3D-NoC mapping. GECCO (Companion) (2013)
Carlos Ivan Castro Marquez, Marius Strum, Jiang Chau Wang
Formal equivalence checking between high-level and RTL hardware designs. LATW (2013)
Joel Ivan Munoz Quispe, Marius Strum, Jiang Chau Wang
PrOCov: Probabilistic output coverage model. LATW (2013)
Jorge González, Gustavo Patino Alvarez, Marius Strum, Wang Jiang Chau
Long range dependence in intrachip transaction level traffic. LASCAS (2013)
Johanna Sepúlveda, Ricardo Pires, Guy Gogniat, Jiang Chau Wang, Marius Strum
QoSS Hierarchical NoC-Based Architecture for MPSoC Dynamic Protection. Int. J. Reconfigurable Comput. 2012 (2012)
Martha Johanna Sepúlveda, Jiang Chau Wang, Marius Strum, César Pedraza, Guy Gogniat, Ricardo Pires
Multi-objective artificial immune algorithm for security-constrained multi-application NoC mapping. GECCO (Companion) (2012)
Gustavo Patino Alvarez, Jorge González, Jiang Chau Wang, Marius Strum
Workload and task characterization based on operation modes timing analysis. SoCC (2012)
Johanna Sepúlveda, Guy Gogniat, Ricardo Pires, Jiang Chau Wang, Marius Strum
Hybrid-on-chip communication architecture for dynamic MP-SoC protection. SBCCI (2012)
Carlos Ivan Castro Marquez, Marius Strum, Wang Jiang Chau, Fabian Vargas
Formally verifying an RTOS scheduling monitor IP core in embedded systems. LATW (2011)
Carlos Ivan Castro Marquez, Edgar Leonardo Romero Tobar, Marius Strum, Jiang Chau Wang
A Functional Verification Methodology Based on Parameter Domains for Efficient Input Stimuli Generation and Coverage Modeling. J. Electron. Test. 27 (4) (2011)
Johanna Sepúlveda, Guy Gogniat, Ricardo Pires, Jiang Chau Wang, Marius Strum
Dynamic NoC-based architecture for MPSoC security implementation. SBCCI (2011)
Johanna Sepúlveda, Marius Strum, Jiang Chau Wang, Ricardo Pires
The LRD traffic impact on the NoC-based SoCs. SBCCI (2010)
Carlos Ivan Castro Marquez, Marius Strum, Wang Jiang Chau
Automatic generation of a parameter-domain-based functional input coverage model. LATW (2010)
Johanna Sepúlveda, Ricardo Pires, Marius Strum, Jiang Chau Wang
Implementation of QoSS (Quality-of-Security Service) for NoC-Based SoC Protection. Trans. Comput. Sci. 10 (2010)
Raul Acosta Hernandez, Marius Strum, Jiang Chau Wang, Jose Artur Quilici González
The Multiple Pairs SMO: A modified SMO algorithm for the acceleration of the SVM training. IJCNN (2009)
Carlos Ivan Castro Marquez, Marius Strum, Jiang Chau Wang
A PD-based methodology to enhance efficiency in testbenches with random stimulation. SBCCI (2009)
Duarte Lopes de Oliveira, Marius Strum, Sandro S. Sato
Burst-Mode Asynchronous Controllers on FPGA. Int. J. Reconfigurable Comput. 2008 (2008)
Frederico De Faria, Marius Strum, Jiang Chau Wang
A System-level Performance Evaluation Methodology for Network Processors Based on Network Calculus Analytical Modeling. ISVLSI (2007)
John Esquiagola, Guilherme Ozari, Marcio Yukio Teruya, Marius Strum, Jiang Chau Wang
A Dynamically Reconfigurable Bluetooth Base Band Unit. FPL (2005)
Duarte Lopes de Oliveira, Marius Strum, Jiang Chau Wang
Miriã_SI: a tool for the synthesis of speed-independent multi burst-mode controllers. SBCCI (2005)
Edgar Leonardo Romero, Marius Strum, Jiang Chau Wang
Comparing two testbench methods for hierarchical functional verification of a bluetooth baseband adaptor. CODES+ISSS (2005)
Jiang Chau Wang, Paulo Sérgio Cardoso, Jose Artur Quilici González, Marius Strum, Ricardo Pires
Datapath BIST Insertion Using Pre-Characterized Area and Testability Data. J. Electron. Test. 20 (4) (2004)
Ivan Jeukens, Marius Strum
Exploring Models of Computation through Static Analysis. FDL (2003)
Duarte Lopes de Oliveira, Marius Strum, Jiang Chau Wang, W. C. Cunha
Miriã: a CAD tool to synthesize multi-burst controllers for heterogeneous systems. Microelectron. Reliab. 43 (2) (2003)
João Martins, Marius Strum
Power Management Exploration for a Block Turbo Decoder. SBCCI (2002)
Wang Jiang Chau, Paulo Sérgio Cardoso, Marius Strum, Ricardo Pires
A Comparison Between Test Pattern Generation Strategies for Functional Units in BIST Applications. LATW (2002)
Wang Jiang Chau, Jose Artur Quilici González, Marius Strum, Ricardo Pires
BIST Plan Optimization and Independent Input Test Register Insertion for Datapath Functional Units. LATW (2002)
Duarte Lopes de Oliveira, Wagner Chiepa Cunha, Marius Strum, Wang Jiang Chau
Synthesis of Multi-Burst Controllers as Modified Huffman Machines. SBCCI (2001)
Jose Artur Quilici González, José Roberto de A. Amazonas, Marius Strum, Wang Jiang Chau
Self Test Built-in Plan for Data-Path Functional Units. LATW (2000)
Duarte Lopes de Oliveira, Marius Strum, Wang Jiang Chau, Wagner Chiepa Cunha
Synthesis of High Performance Extended Burst Mode Asynchronous State Machines. SBCCI (2000)
Ivan Jeukens, Marius Strum
On the Choice of Models of Computation for Writing Executable Specifications of System Level Designs. SBCCI (2000)
Carlos Humberto Llanos Quintero, Marius Strum
SINMEF - A Decomposition Based Synthesis Tool for Large FSMs. Great Lakes Symposium on VLSI (1999)
Marcio Yukio Teruya, Marius Strum, Jiang Chau Wang
Architectural Transformations for Hierarchical Algorithmic Descriptions. VLSI (1999)
José Roberto de A. Amazonas, Marius Strum, Wang Jiang Chau
Exploring Concurrency in Data Path Functional Units BIST Plan Optimization: A Study-Case. SBCCI (1998)
Paulo Sérgio Cardoso, Marius Strum, José Roberto de A. Amazonas, Jiang Chau Wang
A Methodology for Minimum Area Cellular Automata Generation. Asian Test Symposium (1998)