Login / Signup
A Unified Sequential Equivalence Checking Methodology to Verify RTL Designs with High-Level Functional and Protocol Specification Models.
Carlos Ivan Castro Marquez
Marius Strum
Jiang Chau Wang
Published in:
J. Electron. Test. (2015)
Keyphrases
</>
high level
low level
machine learning
artificial intelligence
data streams
design process
formal specification