Jiang Chau Wang

Publication Activity (10 Years)

Years Active: 1995-2018
Publications (10 Years): 5

Top Topics

Hardware Designs

Routing Algorithm

Network On Chip

Top Venues

GECCO (Companion)

Publications

Vinicius Martins, Jerson Paulo Guex, Luciana Shiroma Montali, Jiang Chau Wang
The functional verification of a satellite transponder. LASCAS (2018)
Jose Eduardo Chiarelli Bueno Filho, Jiang Chau Wang
Multifractal on-chip traffic generation under TLM. SoCC (2017)
Vinicius Martins, Jiang Chau Wang, Jerson Paulo Guex
Mixed signal verification to avoid integration mismatch in complex SoCs. LATS (2017)
Jose Eduardo Chiarelli Bueno Filho, Jorge Luis Gonzalez Reano, Jiang Chau Wang
Intra-chip traffic generation under autoregressive models based on time series obtained by TLM simulation. SoCC (2016)
Gustavo Patino Alvarez, Jiang Chau Wang
Scenario-Aware Workload Characterization Based on a Max-Plus Linear Representation. FORMATS (2016)
Raul Acosta Hernandez, Marius Strum, Jiang Chau Wang
Transformations on the FSMD of the RTL code with combinational logic statements for equivalence checking of HLS. LATS (2015)
Carlos Ivan Castro Marquez, Marius Strum, Jiang Chau Wang
A Unified Sequential Equivalence Checking Methodology to Verify RTL Designs with High-Level Functional and Protocol Specification Models. J. Electron. Test. 31 (3) (2015)
Ernesto Villegas Castillo, Gabriele Miorandi, Davide Bertozzi, Jiang Chau Wang
DyAFNoC: Dynamically Reconfigurable NoC Characterization Using a Simple Adaptive Deadlock-Free Routing Algorithm with a Low Implementation Cost. ARC (2015)
Ernesto Villegas Castillo, Jiang Chau Wang, Gabriele Miorandi, Davide Bertozzi
Dynamically Reconfigurable NoC using a deadlock-free flexible routing algorithm with a low hardware implementation cost. LASCAS (2015)
Jonas Gomes Filho, Marius Strum, Jiang Chau Wang
Using Genetic Algorithms for Hardware Core Placement and Mapping in NoC-Based Reconfigurable Systems. Int. J. Reconfigurable Comput. 2015 (2015)
Ernesto Villegas Castillo, Gabriele Miorandi, Jiang Chau Wang
DyAFNoC: Characterization and analysis of a dynamically reconfigurable NoC using a DOR-based deadlock-free routing algorithm. NOCS (2014)
Carlos Ivan Castro Marquez, Marius Strum, Jiang Chau Wang
A unified sequential equivalence checking approach to verify high-level functionality and protocol specification implementations in RTL designs. LATW (2014)
Jonas Gomes Filho, Jiang Chau Wang
Exploring the problems of placement and mapping in NoC-based reconfizurable systems. ReConFig (2013)
Johanna Sepúlveda, Guy Gogniat, Ricardo Pires, Jiang Chau Wang, Marius Strum
Security-enhanced 3D communication structure for dynamic 3D-MPSoCs protection. SBCCI (2013)
Edgar Leonardo Romero, Marius Strum, Jiang Chau Wang
Manipulation of Training Sets for Improving Data Mining Coverage-Driven Verification. J. Electron. Test. 29 (2) (2013)
Carlos Ivan Castro Marquez, Marius Strum, Jiang Chau Wang
Functional verification of complete sequential behaviors: A formal treatment of discrepancies between system-level and RTL descriptions. IDT (2013)
Johanna Sepúlveda, Guy Gogniat, Ricardo Pires, Jiang Chau Wang, Marius Strum
An evolutive approach for designing thermal and performance-aware heterogeneous 3D-NoCs. SBCCI (2013)
Martha Johanna Sepúlveda, Guy Gogniat, Daniel Mauricio Sepúlveda, Ricardo Pires, Jiang Chau Wang, Marius Strum
3DMIA: a multi-objective artificial immune algorithm for 3D-MPSoC multi-application 3D-NoC mapping. GECCO (Companion) (2013)
Carlos Ivan Castro Marquez, Marius Strum, Jiang Chau Wang
Formal equivalence checking between high-level and RTL hardware designs. LATW (2013)
Joel Ivan Munoz Quispe, Marius Strum, Jiang Chau Wang
PrOCov: Probabilistic output coverage model. LATW (2013)
Johanna Sepúlveda, Ricardo Pires, Guy Gogniat, Jiang Chau Wang, Marius Strum
QoSS Hierarchical NoC-Based Architecture for MPSoC Dynamic Protection. Int. J. Reconfigurable Comput. 2012 (2012)
Martha Johanna Sepúlveda, Jiang Chau Wang, Marius Strum, César Pedraza, Guy Gogniat, Ricardo Pires
Multi-objective artificial immune algorithm for security-constrained multi-application NoC mapping. GECCO (Companion) (2012)
Gustavo Patino Alvarez, Jorge González, Jiang Chau Wang, Marius Strum
Workload and task characterization based on operation modes timing analysis. SoCC (2012)
Johanna Sepúlveda, Guy Gogniat, Ricardo Pires, Jiang Chau Wang, Marius Strum
Hybrid-on-chip communication architecture for dynamic MP-SoC protection. SBCCI (2012)
Carlos Ivan Castro Marquez, Edgar Leonardo Romero Tobar, Marius Strum, Jiang Chau Wang
A Functional Verification Methodology Based on Parameter Domains for Efficient Input Stimuli Generation and Coverage Modeling. J. Electron. Test. 27 (4) (2011)
Johanna Sepúlveda, Guy Gogniat, Ricardo Pires, Jiang Chau Wang, Marius Strum
Dynamic NoC-based architecture for MPSoC security implementation. SBCCI (2011)
Johanna Sepúlveda, Marius Strum, Jiang Chau Wang, Ricardo Pires
The LRD traffic impact on the NoC-based SoCs. SBCCI (2010)
Johanna Sepúlveda, Ricardo Pires, Marius Strum, Jiang Chau Wang
Implementation of QoSS (Quality-of-Security Service) for NoC-Based SoC Protection. Trans. Comput. Sci. 10 (2010)
Raul Acosta Hernandez, Marius Strum, Jiang Chau Wang, Jose Artur Quilici González
The Multiple Pairs SMO: A modified SMO algorithm for the acceleration of the SVM training. IJCNN (2009)
Carlos Ivan Castro Marquez, Marius Strum, Jiang Chau Wang
A PD-based methodology to enhance efficiency in testbenches with random stimulation. SBCCI (2009)
Frederico De Faria, Marius Strum, Jiang Chau Wang
A System-level Performance Evaluation Methodology for Network Processors Based on Network Calculus Analytical Modeling. ISVLSI (2007)
John Esquiagola, Guilherme Ozari, Marcio Yukio Teruya, Marius Strum, Jiang Chau Wang
A Dynamically Reconfigurable Bluetooth Base Band Unit. FPL (2005)
Duarte Lopes de Oliveira, Marius Strum, Jiang Chau Wang
Miriã_SI: a tool for the synthesis of speed-independent multi burst-mode controllers. SBCCI (2005)
Edgar Leonardo Romero, Marius Strum, Jiang Chau Wang
Comparing two testbench methods for hierarchical functional verification of a bluetooth baseband adaptor. CODES+ISSS (2005)
Jiang Chau Wang, Paulo Sérgio Cardoso, Jose Artur Quilici González, Marius Strum, Ricardo Pires
Datapath BIST Insertion Using Pre-Characterized Area and Testability Data. J. Electron. Test. 20 (4) (2004)
Duarte Lopes de Oliveira, Marius Strum, Jiang Chau Wang, W. C. Cunha
Miriã: a CAD tool to synthesize multi-burst controllers for heterogeneous systems. Microelectron. Reliab. 43 (2) (2003)
Marcio Yukio Teruya, Marius Strum, Jiang Chau Wang
Architectural Transformations for Hierarchical Algorithmic Descriptions. VLSI (1999)
Paulo Sérgio Cardoso, Marius Strum, José Roberto de A. Amazonas, Jiang Chau Wang
A Methodology for Minimum Area Cellular Automata Generation. Asian Test Symposium (1998)
Jiang Chau Wang, Edward P. Stabler
Collective Test Generation and Test Set Compaction. ISCAS (1995)