Duarte Lopes de Oliveira

Publication Activity (10 Years)

Years Active: 2000-2023
Publications (10 Years): 24

Top Topics

Delay Insensitive

Fpga Implementation

Asynchronous Circuits

Top Venues

Microelectron. J.

Publications

Duarte Lopes de Oliveira, Marcus H. Victor, Luiz C. Moreira, Felipe F. Nascimento
Design of Quasi Delay Insensitive Combinational Circuits Based on Optimized DIMS. LASCAS (2023)
Orlando Verducci Jr., Duarte Lopes de Oliveira, Gracieth Cavalcanti Batista
Fault-Tolerant Finite State Machine Quasi Delay Insensitive in Commercial FPGA Devices. LASCAS (2022)
Gabriel C. Duarte, Duarte Lopes de Oliveira, Gracieth Cavalcanti Batista
Design of Asynchronous Pipelines with QDI Template Using Commercial FPGA. LASCAS (2022)
Orlando Verducci Jr., Duarte Lopes de Oliveira, Gracieth Cavalcanti Batista, Tiago S. Curtinhas
A novel approach for the design of low-power pipelined synchronous systems operating in double-edge of the clock. Microelectron. J. 107 (2021)
Gracieth Cavalcanti Batista, Duarte Lopes de Oliveira, Osamu Saotome
New Low-Power Architectures of Support Vector Machine Classifier for Speech Recognition System. LASCAS (2021)
Orlando Verducci Jr., Duarte Lopes de Oliveira, Robson L. Moreno
Fault-Tolerant Quasi Delay Insensitive Combinational Circuits in Commercial FPGA Devices. LATS (2021)
Duarte Lopes de Oliveira, Gabriel C. Duarte, Gracieth Cavalcanti Batista
A New QDI Asynchronous Pipeline with Two-Phase Delay-Insensitive Global Communication. LASCAS (2021)
Duarte Lopes de Oliveira, Gabriel C. Duarte, Nicolly N. M. Cardoso, Gracieth Cavalcanti Batista
Implementation of Asynchronous Pipelines with QDI Template onto FPGAs Using Commercial Tools. SBCCI (2020)
Duarte Lopes de Oliveira, Gabriel C. Duarte, Gracieth Cavalcanti Batista, Diego A. Silva, Leonardo Romano
Synthesis of Asynchronous State Machines from Synchronous Specifications. LASCAS (2020)
Gracieth Cavalcanti Batista, Duarte Lopes de Oliveira, Osamu Saotome, Washington Luis Santos Silva
A low-power asynchronous hardware implementation of a novel SVM classifier, with an application in a speech recognition system. Microelectron. J. 105 (2020)
Duarte Lopes de Oliveira, Orlando Verducci Jr., Vitor L. V. Torres, Gracieth Cavalcanti Batista, Robson L. Moreno, Leonardo Romano
An Implementation of Extended Burst-Mode Specifications as Quasi Delay Insensitive State Machines. LASCAS (2019)
Tiago S. Curtinhas, Duarte Lopes de Oliveira, Gracieth Cavalcanti Batista, Vitor L. V. Torres, Leonardo Romano
A State Assignment Method for Extended Burst-Mode gC Finite State Machines Based on Genetic Algorithm. LASCAS (2019)
Diego A. Silva, Orlando Verducci Jr., Duarte Lopes de Oliveira
Implementation of DES Algorithm in New Non-Synchronous Architecture Aiming DPA Robustness. VLSI-SoC (2019)
Higor A. Delsoto, Duarte Lopes de Oliveira, Gracieth Cavalcanti Batista, Diego A. Silva, Leonardo Romano
A Tools Flow for Synthesis of Asynchronous Control Circuits from Extended STG Specifications. LASCAS (2019)
Gracieth Cavalcanti Batista, Washington Luis Santos Silva, Duarte Lopes de Oliveira, Osamu Saotome
Automatic speech patterns recognition of commands using SVM and PSO. Multim. Tools Appl. 78 (22) (2019)
Higor A. Delsoto, Duarte Lopes de Oliveira, Lucas M. Santana, Lester de Abreu Faria
A design flow of asynchronous burst-mode circuits without fundamental-mode timing assumption. LASCAS (2018)
Duarte Lopes de Oliveira, Kledermon Garcia, Lucas M. Santana, Lester de Abreu Faria
FPGA implementation of high-performance asynchronous pipelines with robust control. LASCAS (2018)
Duarte Lopes de Oliveira, Tiago S. Curtinhas, Lucas M. Santana, Lester de Abreu Faria
A novel state assignment method for XBM AFSMs without the essential hazard assumption. LASCAS (2018)
Felipe Mendes, Tiago S. Curtinhas, Duarte Lopes de Oliveira, Higor A. Delsoto, Lester de Abreu Faria
A Novel Tool for Synthesis by Direct Mapping of Asynchronous Circuits from Extended STG Specifications. VLSI Design (2018)
Gabriel Antonio Fanelli de Souza, Rodrigo Bispo dos Santos, Paloma M. S. Rocha Rizol, Duarte Lopes de Oliveira, Lester de Abreu Faria
A novel fully-programmable analog fuzzifier architecture for interval type-2 fuzzy controllers using current steering mirrors. J. Intell. Fuzzy Syst. 34 (1) (2018)
Felipe Tuyama De Faria Barbosa, Duarte Lopes de Oliveira, Tiago S. Curtinhas, Lester de Abreu Faria, Jocemar Francisco De Souza Luciano
Implementation of Locally-Clocked XBM State Machines on FPGAs Using Synchronous CAD Tools. IEEE Trans. Circuits Syst. I Regul. Pap. (5) (2017)
Kledermon Garcia, Duarte Lopes de Oliveira, Roberto d'Amore, Lester de Abreu Faria, Joao Luis V. Oliveira
FPGA implementation of optimized XBM specifications by transformation for AFSMs. ReConFig (2016)
Duarte Lopes de Oliveira, Felipe Tuyama De Faria Barbosa, Tiago S. Curtinhas, Lester de Abreu Faria, Jocemar F. Sousa
A design flow for locally-clocked XBM asynchronous state machines using synchronous CAD tools. LASCAS (2016)
Eduardo Lussari, Duarte Lopes de Oliveira, Lester de Abreu Faria, Orlando Verducci Jr.
Software-Defined Radio design based on GALS architecture for FPGAs. SBCCI (2016)
Duarte Lopes de Oliveira, Tiago S. Curtinhas, Lester de Abreu Faria, Leonardo Romano
A novel asynchronous interface with pausible clock for partitioned synchronous modules. LASCAS (2015)
Tiago S. Curtinhas, Tassio Cortes Cavalcante, Duarte Lopes de Oliveira, Lester de Abreu Faria, Osamu Saotome
Minimization and Encoding of High Performance Asynchronous State Machines Based on Genetic Algorithm. SBCCI (2015)
Duarte Lopes de Oliveira, Kledermon Garcia, Roberto d'Amore
Using FPGAs to implement asynchronous pipelines. LASCAS (2014)
Tiago S. Curtinhas, Duarte Lopes de Oliveira, Lester de Abreu Faria, Osamu Saotome
A novel State Assignment method for Extended Burst-Mode FSM design using Genetic Algorithm. SBCCI (2014)
Tiago S. Curtinhas, Duarte Lopes de Oliveira, Diego Bompean, Lester de Abreu Faria, Leonardo Romano
SICARELO: A tool for synthesis of locally-clocked extended burst-mode asynchronous Controllers. LASCAS (2014)
Duarte Lopes de Oliveira, Diego Bompean, Tiago S. Curtinhas, Lester de Abreu Faria
Design of locally-clocked asynchronous finite state machines using synchronous CAD tools. LASCAS (2013)
Duarte Lopes de Oliveira, Tiago S. Curtinhas, Lester de Abreu Faria, Leonardo Romano
Design of synchronous pipeline digital systems operating in double-edge of the clock. LASCAS (2013)
Duarte Lopes de Oliveira, Diego Bompean, Lester de Abreu Faria, Joao Luis V. Oliveira
Design of asynchronous systems on FPGA using direct mapping and synchronous specification. ReConFig (2013)
Duarte Lopes de Oliveira, Marius Strum, Sandro S. Sato
Burst-Mode Asynchronous Controllers on FPGA. Int. J. Reconfigurable Comput. 2008 (2008)
Duarte Lopes de Oliveira, Marius Strum, Jiang Chau Wang
Miriã_SI: a tool for the synthesis of speed-independent multi burst-mode controllers. SBCCI (2005)
Duarte Lopes de Oliveira, Marius Strum, Jiang Chau Wang, W. C. Cunha
Miriã: a CAD tool to synthesize multi-burst controllers for heterogeneous systems. Microelectron. Reliab. 43 (2) (2003)
Duarte Lopes de Oliveira, Wagner Chiepa Cunha, Marius Strum, Wang Jiang Chau
Synthesis of Multi-Burst Controllers as Modified Huffman Machines. SBCCI (2001)
Duarte Lopes de Oliveira, Marius Strum, Wang Jiang Chau, Wagner Chiepa Cunha
Synthesis of High Performance Extended Burst Mode Asynchronous State Machines. SBCCI (2000)