A novel approach for the design of low-power pipelined synchronous systems operating in double-edge of the clock.
Orlando Verducci Jr.Duarte Lopes de OliveiraGracieth Cavalcanti BatistaTiago S. CurtinhasPublished in: Microelectron. J. (2021)
Keyphrases
- low power
- power consumption
- high speed
- single chip
- logic circuits
- low power consumption
- vlsi architecture
- power reduction
- low cost
- digital signal processing
- power dissipation
- mixed signal
- gate array
- embedded systems
- delay insensitive
- nm technology
- cmos technology
- digital circuits
- high power
- wireless transmission
- design methodology
- design process
- ultra low power