A low-power asynchronous hardware implementation of a novel SVM classifier, with an application in a speech recognition system.
Gracieth Cavalcanti BatistaDuarte Lopes de OliveiraOsamu SaotomeWashington Luis Santos SilvaPublished in: Microelectron. J. (2020)
Keyphrases
- hardware implementation
- svm classifier
- low power
- power consumption
- delay insensitive
- high speed
- support vector machine
- low cost
- shift register
- support vector machine svm
- image classification
- support vector
- signal processing
- efficient implementation
- kernel function
- feature vectors
- single chip
- logic circuits
- training set
- low power consumption
- image processing algorithms
- software implementation
- gate array
- vlsi circuits
- cmos technology
- svm classification
- semi supervised
- field programmable gate array
- general purpose processors
- object recognition
- image processing
- feature selection
- learning algorithm