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A design flow of asynchronous burst-mode circuits without fundamental-mode timing assumption.
Higor A. Delsoto
Duarte Lopes de Oliveira
Lucas M. Santana
Lester de Abreu Faria
Published in:
LASCAS (2018)
Keyphrases
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high level synthesis
user interface
asynchronous circuits
design process
circuit design
delay insensitive
logic synthesis
real time
genetic algorithm
multi agent
optical flow
user experience
flow field
engineering design
power dissipation
cmos technology