Jerzy J. Dabrowski

Publication Activity (10 Years)

Years Active: 1992-2020
Publications (10 Years): 7

Top Topics

Multivariate Regression

Top Venues

IEEE J. Emerg. Sel. Topics Circuits Syst.

IEEE Trans. Circuits Syst. II Express Briefs

J. Electron. Test.

Publications

Shakeel Ahmad, Jerzy J. Dabrowski
One-Bit ΣΔ-Encoded Stimulus Generation for On-Chip ADC Test. J. Circuits Syst. Comput. 29 (15) (2020)
Shakeel Ahmad, Jerzy J. Dabrowski
Design of Two-Tone RF Generator for On-Chip IP3/IP2 Test. J. Electron. Test. 35 (1) (2019)
Fahad Qazi, Quoc-Tai Duong, Jerzy J. Dabrowski
Tunable selective receiver front end with impedance transformation filtering. Int. J. Circuit Theory Appl. 44 (5) (2016)
Rashad Ramzan, Jerzy J. Dabrowski
RF calibration of on-chip DfT chain by DC stimuli and statistical multivariate regression technique. Integr. 49 (2015)
Fahad Qazi, Jerzy J. Dabrowski
Clock phase imbalance and phase noise in RF N-path filters. ECCTD (2015)
Fahad Qazi, Jerzy J. Dabrowski
Passive SC Sigma Delta Modulators Revisited: Analysis and Design Study. IEEE J. Emerg. Sel. Topics Circuits Syst. 5 (4) (2015)
Fahad Quiz, Quoc-Tai Duong, Jerzy J. Dabrowski
Two-Stage Highly Selective Receiver Front End Based on Impedance Transformation Filtering. IEEE Trans. Circuits Syst. II Express Briefs (5) (2015)
Fahad Qazi, Quoc-Tai Duong, Jerzy J. Dabrowski
Blocker and image reject low-IF frontend. ECCTD (2013)
Quoc-Tai Duong, Jerzy J. Dabrowski
Focused calibration for advanced RF test with embedded RF detectors. ECCTD (2013)
Quoc-Tai Duong, Jerzy J. Dabrowski, Atila Alvandpour
Highly linear open-loop output driver design for high speed capacitive DACs. NORCHIP (2013)
Quoc-Tai Duong, Jerzy J. Dabrowski
Wideband RF detector design for high performance on-chip test. NORCHIP (2012)
Shakeel Ahmad, Jerzy J. Dabrowski
On-chip spectral test for high-speed ADCs by ΣΔ technique. ECCTD (2011)
Quoc-Tai Duong, Jerzy J. Dabrowski
Low noise transconductance amplifier design for continuous-time ΣΔ wideband frontend. ECCTD (2011)
Shakeel Ahmad, Kaveh Azizi, Iman Esmaeil Zadeh, Jerzy J. Dabrowski
Two-tone PLL for on-chip IP3 test. ISCAS (2010)
Rashad Ramzan, N. Ahsan, Jerzy J. Dabrowski
On-Chip Stimulus Generator for Gain, Linearity, and Blocking Profile Test of Wideband RF Front Ends. IEEE Trans. Instrum. Meas. 59 (11) (2010)
Jerzy J. Dabrowski, Rashad Ramzan
Built-in Loopback Test for IC RF Transceivers. IEEE Trans. Very Large Scale Integr. Syst. 18 (6) (2010)
Shakeel Ahmad, Jerzy J. Dabrowski
On-chip stimuli generation for ADC dynamic test by ΣΔ technique. ECCTD (2009)
Jerzy J. Dabrowski, Rashad Ramzan
Interactive presentation: Boosting SER test for RF transceivers by simple DSP technique. DATE (2007)
Stefan Back Andersson, Rashad Ramzan, Jerzy J. Dabrowski, Christer Svensson
Multiband direct RF-sampling receiver front-end for WLAN in 0.13 μm CMOS. ECCTD (2007)
Rashad Ramzan, Stefan Back Andersson, Jerzy J. Dabrowski, Christer Svensson
A 1.4V 25mW Inductorless Wideband LNA in 0.13μm CMOS. ISSCC (2007)
Stefan Back Andersson, Jerzy J. Dabrowski, Christer Svensson, J. Konopacki
SC filter for RF down conversion with wideband image rejection. ISCAS (2006)
Rashad Ramzan, Lei Zou, Jerzy J. Dabrowski
LNA design for on-chip RF test. ISCAS (2006)
Darius Jakonis, Kalle Folkesson, Jerzy J. Dabrowski, Patrik Eriksson, Christer Svensson
A 2.4-GHz RF sampling receiver front-end in 0.18-/spl mu/m CMOS. IEEE J. Solid State Circuits 40 (6) (2005)
Jerzy J. Dabrowski, Javier Gonzalez Bayon
Techniques for sensitizing RF path under SER test. ISCAS (5) (2005)
Jerzy J. Dabrowski, Javier Gonzalez Bayon
Mixed Loopback BiST for RF Digital Transceivers. DFT (2004)
Jerzy J. Dabrowski
Fault modeling of RF blocks based on noise analysis. ISCAS (1) (2004)
Jerzy J. Dabrowski
Lookback BiST for RF front-ends in digital transceivers. SoC (2003)
Jerzy J. Dabrowski
BiST Model for IC RF-Transceiver Front-End. DFT (2003)
Jerzy J. Dabrowski
Efficient post-layout timing verification via RLC trees and explicit PWL timing integration. ICECS (2002)
Jerzy J. Dabrowski
Efficient interconnect timing analysis via piecewise linear technique. ISCAS (2000)
Jerzy J. Dabrowski, Andrzej Pulka
Experiences with Modeling of Analog and Mixed A/D Systems Based on PWL Technique. DATE (1999)
Jerzy J. Dabrowski
Functional-level analog macromodeling with piecewise linear signals. EURO-DAC (1995)
Jerzy J. Dabrowski
Efficient timing verification via mixed-mode technique. Microprocess. Microprogramming 34 (1-5) (1992)